Mesa (master): intel/compiler: Do not reswizzle dst if instruction writes to flag register

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Module: Mesa
Branch: master
Commit: 04508f57d1d36587f3cc048f0f5dae0611f9330c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=04508f57d1d36587f3cc048f0f5dae0611f9330c

Author: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Date:   Mon Mar 25 14:15:27 2019 +0200

intel/compiler: Do not reswizzle dst if instruction writes to flag register

If we write to the flag register changing the swizzle would change
what channels are written to the flag register.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110201
Fixes: 4cd1a0be
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Reviewed-by: <ian.d.romanick at intel.com>

---

 src/intel/compiler/brw_vec4.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index bb8b554c852..7d60665b621 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1154,6 +1154,12 @@ vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo,
    if (devinfo->gen == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW)
       return false;
 
+   /* If we write to the flag register changing the swizzle would change
+    * what channels are written to the flag register.
+    */
+   if (writes_flag())
+      return false;
+
    /* We can't swizzle implicit accumulator access.  We'd have to
     * reswizzle the producer of the accumulator value in addition
     * to the consumer (i.e. both MUL and MACH).  Just skip this.