Mesa (staging/19.0): intel/compiler: Do not reswizzle dst if instruction writes to flag register
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Tue Apr 16 18:18:24 UTC 2019
Module: Mesa
Branch: staging/19.0
Commit: bde36e0736c113fbf4a8f69a64d5f817d6d5b0a8
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bde36e0736c113fbf4a8f69a64d5f817d6d5b0a8
Author: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Date: Mon Mar 25 14:15:27 2019 +0200
intel/compiler: Do not reswizzle dst if instruction writes to flag register
If we write to the flag register changing the swizzle would change
what channels are written to the flag register.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110201
Fixes: 4cd1a0be
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Reviewed-by: <ian.d.romanick at intel.com>
(cherry picked from commit 04508f57d1d36587f3cc048f0f5dae0611f9330c)
---
src/intel/compiler/brw_vec4.cpp | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 4489c682d01..785508f1e3f 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1160,6 +1160,12 @@ vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo,
if (devinfo->gen == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW)
return false;
+ /* If we write to the flag register changing the swizzle would change
+ * what channels are written to the flag register.
+ */
+ if (writes_flag())
+ return false;
+
/* We can't swizzle implicit accumulator access. We'd have to
* reswizzle the producer of the accumulator value in addition
* to the consumer (i.e. both MUL and MACH). Just skip this.
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