Mesa (master): virgl: simplify virgl_texture_transfer_unmap logic

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Module: Mesa
Branch: master
Commit: b08e73308ec23399def414c6f6d5020496ffda9a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b08e73308ec23399def414c6f6d5020496ffda9a

Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date:   Thu Apr  4 16:50:18 2019 +0200

virgl: simplify virgl_texture_transfer_unmap logic

There's no reason to keep an extra indentation level here, let's merge
the two if-conditions.

Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>

---

 src/gallium/drivers/virgl/virgl_texture.c | 22 +++++++++-------------
 1 file changed, 9 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_texture.c b/src/gallium/drivers/virgl/virgl_texture.c
index 4d938ca1e0d..a17c0941282 100644
--- a/src/gallium/drivers/virgl/virgl_texture.c
+++ b/src/gallium/drivers/virgl/virgl_texture.c
@@ -174,19 +174,15 @@ static void virgl_texture_transfer_unmap(struct pipe_context *ctx,
    struct virgl_transfer *trans = virgl_transfer(transfer);
    struct virgl_resource *vtex = virgl_resource(transfer->resource);
 
-   if (trans->base.usage & PIPE_TRANSFER_WRITE) {
-      if (!(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT)) {
-         struct virgl_screen *vs = virgl_screen(ctx->screen);
-
-         if (trans->resolve_tmp) {
-            vs->vws->transfer_put(vs->vws, vtex->hw_res,
-                                  &transfer->box, trans->base.stride,
-                                  trans->l_stride, trans->offset,
-                                  transfer->level);
-         } else {
-            virgl_transfer_queue_unmap(&vctx->queue, trans);
-         }
-      }
+   if (transfer->usage & PIPE_TRANSFER_WRITE &&
+       (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) == 0) {
+      if (trans->resolve_tmp) {
+         struct virgl_winsys *vws = virgl_screen(ctx->screen)->vws;
+         vws->transfer_put(vws, vtex->hw_res, &transfer->box,
+                           trans->base.stride, trans->l_stride,
+                           trans->offset, transfer->level);
+      } else
+         virgl_transfer_queue_unmap(&vctx->queue, trans);
    }
 
    if (trans->resolve_tmp) {