Mesa (master): iris: implement WaEnableStateCacheRedirectToCS

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Module: Mesa
Branch: master
Commit: d1be67db39463b48369cb71979ed18662b2c157e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1be67db39463b48369cb71979ed18662b2c157e

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Thu Apr 18 11:57:57 2019 +0100

iris: implement WaEnableStateCacheRedirectToCS

This 3d performance workaround was initially put in the kernel but the
media driver requires different settings so the register has been
whitelisted in i915 [1] and userspace drivers are left initializing it as
they wish.

[1] : https://patchwork.freedesktop.org/series/59494/

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>

---

 src/gallium/drivers/iris/iris_state.c | 7 +++++++
 src/intel/genxml/gen11.xml            | 5 +++++
 2 files changed, 12 insertions(+)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 8d5383598d2..2c85ba3778a 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -721,6 +721,13 @@ iris_init_render_context(struct iris_screen *screen,
       }
       iris_emit_lri(batch, COMMON_SLICE_CHICKEN3, reg_val);
 
+      iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1), &reg_val, reg) {
+         reg.StateCacheRedirectToCSSectionEnable = true;
+         reg.StateCacheRedirectToCSSectionEnableMask = true;
+      }
+      iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val);
+
+
       // XXX: 3D_MODE?
 #endif
 
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 83e03f6f7f0..243752abafc 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -7015,6 +7015,11 @@
     <field name="SFBE Done" start="25" end="25" type="bool"/>
   </register>
 
+  <register name="SLICE_COMMON_ECO_CHICKEN1" length="1" num="0x731c">
+    <field name="State Cache Redirect To CS Section Enable" start="11" end="11" type="bool"/>
+    <field name="State Cache Redirect To CS Section Enable Mask" start="27" end="27" type="bool"/>
+  </register>
+
   <register name="SO_NUM_PRIMS_WRITTEN0" length="2" num="0x5200">
     <field name="Num Prims Written Count" start="0" end="63" type="uint"/>
   </register>