Mesa (master): iris: Be less aggressive at postdraw work skipping

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Module: Mesa
Branch: master
Commit: a913fbf124e201a8bf53fe8385619a71a6e9594b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a913fbf124e201a8bf53fe8385619a71a6e9594b

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Apr 18 14:35:26 2019 -0700

iris: Be less aggressive at postdraw work skipping

We empty the cache sets when flushing the batch, at which point we need
to add any framebuffer related BOs even though the bindings haven't
changed.  So, we now do the cache set tracking unconditionally.

For now, we continue skipping resolve work based on the same conditions
in the predraw functions - the thinking is if we didn't trigger
resolves, there's nothing to update here.  Time will tell if this works.

Partly reverts commit 365886ebe1a54f893b688b457553eead6aa572ea, and
fixes Unigine Valley rendering on Gen9+.  Drops drawoverhead scores
by about 10-12%.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110353

---

 src/gallium/drivers/iris/iris_resolve.c | 64 ++++++++++++++++++---------------
 1 file changed, 36 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c
index cff40513073..8555ce67588 100644
--- a/src/gallium/drivers/iris/iris_resolve.c
+++ b/src/gallium/drivers/iris/iris_resolve.c
@@ -248,50 +248,58 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 
    // XXX: front buffer drawing?
 
-   if (ice->state.dirty & (IRIS_DIRTY_DEPTH_BUFFER |
-                           IRIS_DIRTY_WM_DEPTH_STENCIL)) {
-      struct pipe_surface *zs_surf = cso_fb->zsbuf;
-      if (zs_surf) {
-         struct iris_resource *z_res, *s_res;
-         iris_get_depth_stencil_resources(zs_surf->texture, &z_res, &s_res);
-         unsigned num_layers =
-            zs_surf->u.tex.last_layer - zs_surf->u.tex.first_layer + 1;
-
-         if (z_res) {
+   bool may_have_resolved_depth =
+      ice->state.dirty & (IRIS_DIRTY_DEPTH_BUFFER |
+                          IRIS_DIRTY_WM_DEPTH_STENCIL);
+
+   struct pipe_surface *zs_surf = cso_fb->zsbuf;
+   if (zs_surf) {
+      struct iris_resource *z_res, *s_res;
+      iris_get_depth_stencil_resources(zs_surf->texture, &z_res, &s_res);
+      unsigned num_layers =
+         zs_surf->u.tex.last_layer - zs_surf->u.tex.first_layer + 1;
+
+      if (z_res) {
+         if (may_have_resolved_depth) {
             iris_resource_finish_depth(ice, z_res, zs_surf->u.tex.level,
                                        zs_surf->u.tex.first_layer, num_layers,
                                        ice->state.depth_writes_enabled);
-
-            if (ice->state.depth_writes_enabled)
-               iris_depth_cache_add_bo(batch, z_res->bo);
          }
 
-         if (s_res) {
+         if (ice->state.depth_writes_enabled)
+            iris_depth_cache_add_bo(batch, z_res->bo);
+      }
+
+      if (s_res) {
+         if (may_have_resolved_depth) {
             iris_resource_finish_write(ice, s_res, zs_surf->u.tex.level,
                                        zs_surf->u.tex.first_layer, num_layers,
                                        ISL_AUX_USAGE_NONE);
-
-            if (ice->state.stencil_writes_enabled)
-               iris_depth_cache_add_bo(batch, s_res->bo);
          }
+
+         if (ice->state.stencil_writes_enabled)
+            iris_depth_cache_add_bo(batch, s_res->bo);
       }
    }
 
-   if (ice->state.dirty & (IRIS_DIRTY_BINDINGS_FS | IRIS_DIRTY_BLEND_STATE)) {
-      for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
-         struct iris_surface *surf = (void *) cso_fb->cbufs[i];
-         if (!surf)
-            continue;
+   bool may_have_resolved_color =
+      ice->state.dirty & (IRIS_DIRTY_BINDINGS_FS | IRIS_DIRTY_BLEND_STATE);
 
-         struct iris_resource *res = (void *) surf->base.texture;
+   for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
+      struct iris_surface *surf = (void *) cso_fb->cbufs[i];
+      if (!surf)
+         continue;
+
+      struct iris_resource *res = (void *) surf->base.texture;
+      enum isl_aux_usage aux_usage = ice->state.draw_aux_usage[i];
+
+      iris_render_cache_add_bo(batch, res->bo, surf->view.format,
+                               aux_usage);
+
+      if (may_have_resolved_color) {
          union pipe_surface_desc *desc = &surf->base.u;
          unsigned num_layers =
             desc->tex.last_layer - desc->tex.first_layer + 1;
-         enum isl_aux_usage aux_usage = ice->state.draw_aux_usage[i];
-
-         iris_render_cache_add_bo(batch, res->bo, surf->view.format,
-                                  aux_usage);
-
          iris_resource_finish_render(ice, res, desc->tex.level,
                                      desc->tex.first_layer, num_layers,
                                      aux_usage);