Mesa (master): anv: limit URB reconfigurations when using blorp

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Module: Mesa
Branch: master
Commit: 0d46e404677264bfb12ada15290e39c10a5eb455
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d46e404677264bfb12ada15290e39c10a5eb455

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Wed Mar  6 11:42:14 2019 +0000

anv: limit URB reconfigurations when using blorp

If the last graphics pipeline bound to the command buffer has enough
space in its VS URB entries for Blorp then avoid reconfiguring the URB
partitions.

v2: s/0/MESA_SHADER_VERTEX/ (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

---

 src/intel/vulkan/anv_private.h     | 1 +
 src/intel/vulkan/genX_blorp_exec.c | 7 +++++++
 src/intel/vulkan/genX_pipeline.c   | 6 +++---
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 8e733d3a39c..80416ea8f81 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2663,6 +2663,7 @@ struct anv_pipeline {
    struct {
       const struct gen_l3_config *              l3_config;
       uint32_t                                  total_size;
+      unsigned                                  entry_size[4];
    } urb;
 
    VkShaderStageFlags                           active_stages;
diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index 1592e7f7e3d..852353cab2a 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -202,6 +202,13 @@ blorp_emit_urb_config(struct blorp_batch *batch,
 
    assert(sf_entry_size == 0);
 
+   /* If the last used gfx pipeline in the command buffer has enough VS URB
+    * space for what the blorp operation needs, skip reconfiguration.
+    */
+   if (cmd_buffer->state.gfx.base.pipeline &&
+       cmd_buffer->state.gfx.base.pipeline->urb.entry_size[MESA_SHADER_VERTEX] >= vs_entry_size)
+      return;
+
    const unsigned entry_size[4] = { vs_entry_size, 1, 1, 1 };
 
    genX(emit_urb_setup)(device, &cmd_buffer->batch,
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 0b58dce05b0..f2b7faca4a2 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -308,18 +308,18 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
 static void
 emit_urb_setup(struct anv_pipeline *pipeline)
 {
-   unsigned entry_size[4];
    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
       const struct brw_vue_prog_data *prog_data =
          !anv_pipeline_has_stage(pipeline, i) ? NULL :
          (const struct brw_vue_prog_data *) pipeline->shaders[i]->prog_data;
 
-      entry_size[i] = prog_data ? prog_data->urb_entry_size : 1;
+      pipeline->urb.entry_size[i] = prog_data ? prog_data->urb_entry_size : 1;
    }
 
    genX(emit_urb_setup)(pipeline->device, &pipeline->batch,
                         pipeline->urb.l3_config,
-                        pipeline->active_stages, entry_size);
+                        pipeline->active_stages,
+                        pipeline->urb.entry_size);
 }
 
 static void