Mesa (master): 23 new commits

Fri Apr 19 19:57:08 UTC 2019

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ce7c29724082431ed23ced9ec9130bb62c370d2
Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Thu Apr 18 12:08:57 2019 -0500

    anv/nir: Add a central helper for figuring out SSBO address formats
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=470422870a2cd3a235261b8628689c8e93ff3191
Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Thu Apr 18 12:08:34 2019 -0500

    nir: Add helpers for getting the type of an address format
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e230d7607f9b3e082d00859bd7725c4dc87e5cf
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Feb 27 16:08:20 2019 -0600

    anv: Implement VK_EXT_descriptor_indexing
    
    Now that everything is in place to do bindless for all resource types
    except input attachments and UBOs, VK_EXT_descriptor_indexing is
    "trivial".
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6c9bd6e01b4d593f362a3b5518a71acf2e83ca1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Oct 2 15:35:59 2018 -0500

    anv: Put binding flags in descriptor set layouts
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0d9926df7d33ab72b386444569fd0c384b115b8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Feb 12 01:02:28 2019 -0600

    anv: Use bindless handles for images
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=83af92e593ccb316f33fc6a9a7cf8ea0f8ea3486
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Feb 12 00:47:54 2019 -0600

    intel/fs: Add support for bindless image load/store/atomic
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6803f6b6f06e805fe162d76aad5e25d2510232a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Feb 7 14:10:33 2019 -0600

    anv: Use bindless textures and samplers
    
    This commit changes anv to put bindless handles and sampler pointers
    into the descriptor buffer and use those instead of bindful when we run
    out of binding table space.  This "spilling" of descriptors allows to to
    advertise an almost unbounded number of images and samplers.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf61f057f72b57e977440ff66dc557d1140fede3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Feb 8 17:04:07 2019 -0600

    anv: Pass the plane into lower_tex_deref
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f16fcb9db779bd9b48a79df144358ac50428e6e8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Feb 7 22:34:57 2019 -0600

    anv: Use write_image_view to initialize immutable samplers
    
    Instead of setting it manually, call the helper.  When setting
    descriptor sets becomes more complicated than just setting some struct
    values, this will keep immutable sampler handling correct.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e612c3b9bfd5c9bfb6ece9e2b3c88f787d742d85
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Feb 7 10:16:24 2019 -0600

    anv: Count the number of planes in each descriptor binding
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=843286d324c833198f4f5bd6d548ab3612968169
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Feb 6 15:42:17 2019 -0600

    intel/fs: Add support for bindless texture ops
    
    We add two new texture sources for bindless surface and sampler handles.
    Bindless surface handles are expected to be pre-shifted so that the
    20-bit surface state table index is in the top 20 bits of the 32-bit
    handle.  This lets us avoid any extra shifts in the shader.  Bindless
    sampler handles are 32-byte aligned byte offsets from general state base
    address.  We use 32-byte aligned instead of 16-byte aligned to avoid
    having to use more indirect messages than needed.  It means we can't
    tightly pack samplers but that's probably not a big deal.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2edf29b933564d4f1aae80b91f674f1175f91625
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Feb 8 17:56:52 2019 -0600

    intel,nir: Lower TXD with a bindless sampler
    
    When we have a bindless sampler, we need an instruction header.  Even in
    SIMD8, this pushes the instruction over the sampler message size maximum
    of 11 registers.  Instead, we have to lower TXD to TXL.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd56ce8ce5045a181b9fc8a7f24251931e343f9c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Sat Jan 12 18:30:47 2019 -0600

    anv: Implement VK_KHR_shader_atomic_int64
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=79fb0d27f3ab41fec88acbe24bc3163a42c0715c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Jan 9 16:04:22 2019 -0600

    anv: Implement SSBOs bindings with GPU addresses in the descriptor BO
    
    This commit adds a new way for ANV to do SSBO bindings by just passing a
    GPU address in through the descriptor buffer and using the A64 messages
    to access the GPU address directly.  This means that our variable
    pointers are now "real" pointers instead of a vec2(BTI, offset) pair.
    This carries a few of advantages:
    
     1. It lets us support a virtually unbounded number of SSBO bindings.
    
     2. It lets us implement VK_KHR_shader_atomic_int64 which we couldn't
        implement before because those atomic messages are only available
        in the bindless A64 form.
    
     3. It's way better than messing around with bindless handles for SSBOs
        which is the only other option for VK_EXT_descriptor_indexing.
    
     4. It's more future looking, maybe?  At the least, this is what NVIDIA
        does (they don't have binding based SSBOs at all).  This doesn't a
        priori mean it's better, it just means it's probably not terrible.
    
    The big disadvantage, of course, is that we have to start doing our own
    bounds checking for robustBufferAccess again have to push in dynamic
    offsets.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cf78ec2bdc22833082d026d59ccb28d79b07f6f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jan 11 16:52:43 2019 -0600

    anv: Lower some SSBO operations in apply_pipeline_layout
    
    In order to avoid the potential overhead of A64 operations on all SSBO
    ops, we look for those SSBO ops where we can get to the descriptor set
    from the SSBO access operation and lower those to a binding-table
    approach.  When robustBufferAccess is enabled, this lets the hardware do
    the bounds checking for us.  It also avoids some potentially expensive
    64-bit integer calculations.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7a1e8f7356922726ec38326b65e81a99d7ff96e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Feb 7 12:01:18 2019 -0600

    anv: Add a has_a64_buffer_access to anv_physical_device
    
    This is more descriptive and a bit nicer than checking for gen >= 8 &&
    use_softpin everywhere.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1a633d9fb077f1e024f5628ec2034d26cf681b7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jan 10 16:05:06 2019 -0600

    intel/nir: Re-run int64 lowering in postprocess_nir
    
    We're about to start doing 64-bit pointer calculations in ANV.  They
    will get applied after brw_preprocess_nir which is where we currently do
    64-bit integer arithmetic lowering.  Because we're adding 64-bit integer
    arithmetic after the initial lowering has happened, we need to lower
    again.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=995dc4e5c36dad47f5e289e0b1d8095b21729881
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Jan 7 18:00:22 2019 -0600

    nir/lower_io: Expose some explicit I/O lowering helpers
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=146deec9ef5f73794daba4ad7cd95016fd07266a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Feb 25 13:59:07 2019 -0600

    anv/pipeline: Add skeleton support for spilling to bindless
    
    If the number of surfaces or samplers exceeds what we can put in a
    table, we will want to spill out to bindless.  There is no bindless
    support yet but this gets us the basic framework that will be used by
    later commits.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7d48718466978bd5a6ae73d9cf1c2ea566d772c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Feb 20 18:14:56 2019 -0600

    anv/pipeline: Sort bindings by most used first
    
    This commit just sorts the bindings by how often they're used vs the
    array size of the binding.  This will let us make more nuanced decisions
    about what goes in the binding table vs. what to make bindless.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5a0dc08f18928a080e3393ebc694bc7053216fb
Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Tue Apr 16 17:35:05 2019 -0500

    anv: Add a #define for the max binding table size
    
    This also fixes a bug where we mis-calculate maximum binding table sizes
    and may return true in vkGetDescriptorSetLayoutSupport even for sets too
    large to fit in a binding table.
    
    Fixes: ddc40691221 "anv: Implement VK_KHR_maintenance3"
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b755b52e80acc7705775ccaf5f31cf213edb207
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Nov 21 18:26:27 2018 -0600

    anv: Put image params in the descriptor set buffer on gen8 and earlier
    
    This is really where they belong; not push constants.  The one downside
    here is that we can't push them anymore for compute shaders.  However,
    that's a general problem and we should figure out how to push descriptor
    sets for compute shaders.  This lets us bump MAX_IMAGES to 64 on BDW and
    earlier platforms because we no longer have to worry about push constant
    overhead limits.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=83b943cc2f2408087795ee2bd984477a1749a530
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Feb 26 18:05:34 2019 -0600

    anv: Make all VkDeviceMemory BOs resident permanently
    
    We spend a lot of time in the driver adding things to hash sets to track
    residency.  The reality is that a properly built Vulkan app uses large
    memory objects and sub-allocates from them.  In a typical frame, most of
    if not all of those allocations are going to be resident for the entire
    frame so we're really not saving ourselves much by tracking fine-grained
    residency.  Just throwing everything in the validation list does make it
    a little bit more expensive inside the kernel to walk the list and
    ensure that all our VA is in order.  However, without relocations, the
    overhead of that is pretty small.
    
    If we ever do run into a memory pressure situation where the fine-
    grained residency could even potentially help, we would likely be
    swapping one page out to make room for another within the draw call and
    performance is totally lost at that point.  We're better off swapping
    out other apps and just letting ours run a whole frame.
    
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>