Mesa (master): intel/isl: Resize clear color buffer to full cacheline
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Wed Apr 24 06:16:29 UTC 2019
Module: Mesa
Branch: master
Commit: f2041d2a9266ec14270b6da9bf9ce2b54d555ebd
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2041d2a9266ec14270b6da9bf9ce2b54d555ebd
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Tue Apr 16 16:31:06 2019 +0300
intel/isl: Resize clear color buffer to full cacheline
Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI.
v2 (Nanley): In the title s/Align/Resize/
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Tested-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Signed-off-by: Rafael Antognolli <rafael.antognolli at intel.com>
---
src/intel/isl/isl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 6b9e6c9e0f0..acfed5119ba 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -122,7 +122,8 @@ isl_device_init(struct isl_device *dev,
dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
dev->ss.align = isl_align(dev->ss.size, 32);
- dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4;
+ dev->ss.clear_color_state_size =
+ isl_align(CLEAR_COLOR_length(info) * 4, 64);
dev->ss.clear_color_state_offset =
RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;
More information about the mesa-commit
mailing list