Mesa (master): radv: Add support for image views with multiple planes.
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Thu Apr 25 20:08:16 UTC 2019
Module: Mesa
Branch: master
Commit: b2cfa231d0dd46ade036eb76ed0ad55b3f4cf462
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2cfa231d0dd46ade036eb76ed0ad55b3f4cf462
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sun Dec 2 23:58:54 2018 +0100
radv: Add support for image views with multiple planes.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
src/amd/vulkan/radv_descriptor_set.c | 6 +++---
src/amd/vulkan/radv_image.c | 41 ++++++++++++++++++++++--------------
src/amd/vulkan/radv_private.h | 15 +++++++++++--
3 files changed, 41 insertions(+), 21 deletions(-)
diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c
index 7374f94d260..b048f1f7cf9 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -835,12 +835,12 @@ write_image_descriptor(struct radv_device *device,
const VkDescriptorImageInfo *image_info)
{
RADV_FROM_HANDLE(radv_image_view, iview, image_info->imageView);
- uint32_t *descriptor;
+ union radv_descriptor *descriptor;
if (descriptor_type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE) {
- descriptor = iview->storage_descriptor;
+ descriptor = &iview->storage_descriptor;
} else {
- descriptor = iview->descriptor;
+ descriptor = &iview->descriptor;
}
memcpy(dst, descriptor, 16 * 4);
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index dd2c46ae417..a487a5576a6 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -345,11 +345,12 @@ static void
si_set_mutable_tex_desc_fields(struct radv_device *device,
struct radv_image *image,
const struct legacy_surf_level *base_level_info,
+ unsigned plane_id,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
bool is_storage_image, uint32_t *state)
{
- struct radv_image_plane *plane = &image->planes[0];
+ struct radv_image_plane *plane = &image->planes[plane_id];
uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
uint64_t va = gpu_address + plane->offset;
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
@@ -712,7 +713,7 @@ radv_query_opaque_metadata(struct radv_device *device,
image->info.depth,
desc, NULL);
- si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0,
+ si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
image->planes[0].surface.blk_w, false, false, desc);
/* Clear the base address and set the relative DCC offset. */
@@ -1108,31 +1109,34 @@ radv_image_create(VkDevice _device,
static void
radv_image_view_make_descriptor(struct radv_image_view *iview,
struct radv_device *device,
+ VkFormat vk_format,
const VkComponentMapping *components,
- bool is_storage_image, unsigned plane_id)
+ bool is_storage_image, unsigned plane_id,
+ unsigned descriptor_plane_id)
{
struct radv_image *image = iview->image;
struct radv_image_plane *plane = &image->planes[plane_id];
const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
uint32_t blk_w;
- uint32_t *descriptor;
+ union radv_descriptor *descriptor;
uint32_t hw_level = 0;
if (is_storage_image) {
- descriptor = iview->storage_descriptor;
+ descriptor = &iview->storage_descriptor;
} else {
- descriptor = iview->descriptor;
+ descriptor = &iview->descriptor;
}
- assert(plane->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
- blk_w = plane->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
+ assert(vk_format_get_plane_count(vk_format) == 1);
+ assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
+ blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
if (device->physical_device->rad_info.chip_class >= GFX9)
hw_level = iview->base_mip;
si_make_texture_descriptor(device, image, is_storage_image,
iview->type,
- iview->vk_format,
+ vk_format,
components,
hw_level, hw_level + iview->level_count - 1,
iview->base_layer,
@@ -1140,8 +1144,8 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
iview->extent.depth,
- descriptor,
- descriptor + 8);
+ descriptor->plane_descriptors[descriptor_plane_id],
+ descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
const struct legacy_surf_level *base_level_info = NULL;
if (device->physical_device->rad_info.chip_class <= GFX9) {
@@ -1152,9 +1156,10 @@ radv_image_view_make_descriptor(struct radv_image_view *iview,
}
si_set_mutable_tex_desc_fields(device, image,
base_level_info,
+ plane_id,
iview->base_mip,
iview->base_mip,
- blk_w, is_stencil, is_storage_image, descriptor);
+ blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
}
static unsigned
@@ -1212,9 +1217,10 @@ radv_image_view_init(struct radv_image_view *iview,
iview->image = image;
iview->bo = image->bo;
iview->type = pCreateInfo->viewType;
- iview->vk_format = pCreateInfo->format;
- iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
+ iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
+ iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
+ iview->vk_format = pCreateInfo->format;
if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
iview->vk_format = vk_format_stencil_only(iview->vk_format);
@@ -1291,8 +1297,11 @@ radv_image_view_init(struct radv_image_view *iview,
iview->base_mip = range->baseMipLevel;
iview->level_count = radv_get_levelCount(image, range);
- radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false, iview->plane_id);
- radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true, iview->plane_id);
+ for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
+ VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
+ radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
+ radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
+ }
}
bool radv_layout_has_htile(const struct radv_image *image,
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 4bccb88aa17..ddd130773c1 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1670,6 +1670,16 @@ radv_init_metadata(struct radv_device *device,
struct radv_image *image,
struct radeon_bo_metadata *metadata);
+union radv_descriptor {
+ struct {
+ uint32_t plane0_descriptor[8];
+ uint32_t fmask_descriptor[8];
+ };
+ struct {
+ uint32_t plane_descriptors[3][8];
+ };
+};
+
struct radv_image_view {
struct radv_image *image; /**< VkImageViewCreateInfo::image */
struct radeon_winsys_bo *bo;
@@ -1678,18 +1688,19 @@ struct radv_image_view {
VkImageAspectFlags aspect_mask;
VkFormat vk_format;
unsigned plane_id;
+ bool multiple_planes;
uint32_t base_layer;
uint32_t layer_count;
uint32_t base_mip;
uint32_t level_count;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
- uint32_t descriptor[16];
+ union radv_descriptor descriptor;
/* Descriptor for use as a storage image as opposed to a sampled image.
* This has a few differences for cube maps (e.g. type).
*/
- uint32_t storage_descriptor[16];
+ union radv_descriptor storage_descriptor;
};
struct radv_image_create_info {
More information about the mesa-commit
mailing list