Mesa (master): v3d: Fix detection of TMU write sequences in register spilling.
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Fri Apr 26 19:44:09 UTC 2019
Module: Mesa
Branch: master
Commit: fb0611df3d406804da738d599a22da99aa382682
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb0611df3d406804da738d599a22da99aa382682
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 25 12:58:12 2019 -0700
v3d: Fix detection of TMU write sequences in register spilling.
We can't use the QPU functions to detect this until register allocation is
done and we've moved inst->dst into inst->qpu.
Fixes bad TMU sequences from register spilling in
KHR-GLES31.core.compute_shader.shared-max.
---
src/broadcom/compiler/vir_register_allocate.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c
index 1b58bb9c420..7583acf155c 100644
--- a/src/broadcom/compiler/vir_register_allocate.c
+++ b/src/broadcom/compiler/vir_register_allocate.c
@@ -33,6 +33,13 @@
#define PHYS_INDEX (ACC_INDEX + ACC_COUNT)
#define PHYS_COUNT 64
+static inline bool
+qinst_writes_tmu(struct qinst *inst)
+{
+ return (inst->dst.file == QFILE_MAGIC &&
+ v3d_qpu_magic_waddr_is_tmu(inst->dst.index));
+}
+
static bool
is_last_ldtmu(struct qinst *inst, struct qblock *block)
{
@@ -40,7 +47,7 @@ is_last_ldtmu(struct qinst *inst, struct qblock *block)
&block->instructions, link) {
if (scan_inst->qpu.sig.ldtmu)
return false;
- if (v3d_qpu_writes_tmu(&scan_inst->qpu))
+ if (qinst_writes_tmu(scan_inst))
return true;
}
@@ -138,7 +145,7 @@ v3d_choose_spill_node(struct v3d_compile *c, struct ra_graph *g,
inst->qpu.alu.add.op == V3D_QPU_A_TMUWT)
in_tmu_operation = false;
- if (v3d_qpu_writes_tmu(&inst->qpu))
+ if (qinst_writes_tmu(inst))
in_tmu_operation = true;
}
}
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