Mesa (master): Revert "anv: limit URB reconfigurations when using blorp"

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Module: Mesa
Branch: master
Commit: 9628631a380ff24630bf97b982df07b4e7e2a79f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9628631a380ff24630bf97b982df07b4e7e2a79f

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Sat Apr 27 11:35:32 2019 +0800

Revert "anv: limit URB reconfigurations when using blorp"

In commit 0d46e404 ("anv: limit URB reconfigurations when using
blorp") we tried to limit the number of URB reconfiguration by
checking if the last allocation is large enough to fit the blorp
dispatch.

We used the last bound pipeline to compare the allocation. The problem
with this is that the pipeline is bound but its commands might not
have been emitted into the command buffer yet.

Let's just revert commit 0d46e404677264bfb12ada15290e39c10a5eb455
since it didn't seem to yield any performance improvement.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 0d46e404 ("anv: limit URB reconfigurations when using blorp")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110535
Acked-by: Jason Ekstrand <jason at jlekstrand.net>

---

 src/intel/vulkan/anv_private.h     | 1 -
 src/intel/vulkan/genX_blorp_exec.c | 7 -------
 src/intel/vulkan/genX_pipeline.c   | 6 +++---
 3 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 1916104197a..f1875aa7642 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2747,7 +2747,6 @@ struct anv_pipeline {
    struct {
       const struct gen_l3_config *              l3_config;
       uint32_t                                  total_size;
-      unsigned                                  entry_size[4];
    } urb;
 
    VkShaderStageFlags                           active_stages;
diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index 852353cab2a..1592e7f7e3d 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -202,13 +202,6 @@ blorp_emit_urb_config(struct blorp_batch *batch,
 
    assert(sf_entry_size == 0);
 
-   /* If the last used gfx pipeline in the command buffer has enough VS URB
-    * space for what the blorp operation needs, skip reconfiguration.
-    */
-   if (cmd_buffer->state.gfx.base.pipeline &&
-       cmd_buffer->state.gfx.base.pipeline->urb.entry_size[MESA_SHADER_VERTEX] >= vs_entry_size)
-      return;
-
    const unsigned entry_size[4] = { vs_entry_size, 1, 1, 1 };
 
    genX(emit_urb_setup)(device, &cmd_buffer->batch,
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index f2b7faca4a2..0b58dce05b0 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -308,18 +308,18 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
 static void
 emit_urb_setup(struct anv_pipeline *pipeline)
 {
+   unsigned entry_size[4];
    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
       const struct brw_vue_prog_data *prog_data =
          !anv_pipeline_has_stage(pipeline, i) ? NULL :
          (const struct brw_vue_prog_data *) pipeline->shaders[i]->prog_data;
 
-      pipeline->urb.entry_size[i] = prog_data ? prog_data->urb_entry_size : 1;
+      entry_size[i] = prog_data ? prog_data->urb_entry_size : 1;
    }
 
    genX(emit_urb_setup)(pipeline->device, &pipeline->batch,
                         pipeline->urb.l3_config,
-                        pipeline->active_stages,
-                        pipeline->urb.entry_size);
+                        pipeline->active_stages, entry_size);
 }
 
 static void