Mesa (fast-color-clear): i965: Re-enable fast color clears for GEN11.
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Mon Apr 29 17:26:51 UTC 2019
Module: Mesa
Branch: fast-color-clear
Commit: c04f3094fcdfb0bf834ac3a9ffabf90fe0176586
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c04f3094fcdfb0bf834ac3a9ffabf90fe0176586
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Mon Apr 29 20:23:10 2019 +0300
i965: Re-enable fast color clears for GEN11.
This patch re-enables fast color clears for GEN11.
It also ensures that we use linear color formats
for sRGB surfaces during fast clears.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 41 +++++++++++++++++++++++------------
1 file changed, 27 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 3c2445d335d..efa81502ca4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1273,24 +1273,31 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
}
}
- /* FINISHME: Debug and enable fast clears */
- const struct gen_device_info *devinfo = &brw->screen->devinfo;
- if (devinfo->gen >= 11)
- can_fast_clear = false;
-
if (can_fast_clear) {
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ bool clear_color_changed = false;
const enum isl_aux_state aux_state =
intel_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
union isl_color_value clear_color =
brw_meta_convert_fast_clear_color(brw, irb->mt,
&ctx->Color.ClearColor);
- intel_miptree_set_clear_color(brw, irb->mt, clear_color);
+ /* For gen11 we set the clear color in blorp */
+ if (devinfo->gen == 11) {
+ if (memcmp(&irb->mt->fast_clear_color, &clear_color,
+ sizeof(clear_color)) != 0) {
+ irb->mt->fast_clear_color = clear_color;
+ clear_color_changed = true;
+ }
+ } else {
+ clear_color_changed = intel_miptree_set_clear_color(brw, irb->mt,
+ clear_color);
+ }
- /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
- * is redundant and can be skipped.
+ /* If the buffer is already in ISL_AUX_STATE_CLEAR and the clear color
+ * hasn't changed, the clear is redundant and can be skipped.
*/
- if (aux_state == ISL_AUX_STATE_CLEAR)
+ if (aux_state == ISL_AUX_STATE_CLEAR && !clear_color_changed)
return;
DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
@@ -1316,11 +1323,17 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw,
- BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
- blorp_fast_clear(&batch, &surf, isl_format,
- level, irb->mt_layer, num_layers,
- x0, y0, x1, y1);
+ if (devinfo->gen == 11) {
+ blorp_batch_init(&brw->blorp, &batch, brw, 0);
+ blorp_fast_clear(&batch, &surf, isl_format_srgb_to_linear(isl_format),
+ level, irb->mt_layer, num_layers, x0, y0, x1, y1);
+ } else {
+ blorp_batch_init(&brw->blorp, &batch, brw,
+ BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
+ blorp_fast_clear(&batch, &surf, isl_format, level, irb->mt_layer,
+ num_layers, x0, y0, x1, y1);
+ }
+
blorp_batch_finish(&batch);
brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
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