Mesa (fast-color-clear): 56 new commits
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Mon Apr 29 17:29:58 UTC 2019
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=88def55b308a40258d1f079a5750a384e66e69ad
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Mon Apr 29 20:23:10 2019 +0300
i965: Re-enable fast color clears for GEN11.
This patch re-enables fast color clears for GEN11.
It also ensures that we use linear color formats
for sRGB surfaces during fast clears.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=50dd2727cf851f9a90adc34b67b7e99a3945b6ff
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Tue Apr 2 17:08:52 2019 -0700
intel/blorp: Make blorp update the clear color in gen11.
Hardware docs say that Gen11 requires the use of two MI_ATOMICs of size
QWORD when updating the clear color. The second MI_ATOMIC also needs CS
Stall and Return Data Control set.
v2: Remove include of srgb header (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=863627c50e0d384c0f496190391fa2134a6737d5
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Tue Apr 2 17:07:17 2019 -0700
intel/genxml: Update MI_ATOMIC genxml definition.
Change some of the single bit fields to booleans, and add an enum with
the definition of the ATOMIC_OPCODE.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e28fee09d91abd129983a7605c01476926012130
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Apr 19 15:31:29 2019 -0700
intel/genxml: Support base-16 in value & start fields in gen_sort_tags.py
With python's int(), if the optional second parameter is 0, then
python will support the 0x prefix for hex numbers.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=19c4b015792b1cf153891dfdc81ab057185258e9
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Thu Mar 14 22:28:20 2019 +0200
isl: Set ClearColorConversionEnable.
The ClearColorConversionEnable bit needs to be set
for GEN11 when inderect clear colors are used.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd4c661ad08e772fdccb562ffbb2f45705c4fec8
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Apr 25 14:44:40 2019 +0100
ac,ac/nir: use a better sync scope for shared atomics
https://reviews.llvm.org/rL356946 (present in LLVM 9 and later) changed
the meaning of the "system" sync scope, making it no longer restricted to
the memory operation's address space. So a single address space sync scope
is needed for shared atomic operations (such as "system-one-as" or
"workgroup-one-as") otherwise buffer_wbinvl1 and s_waitcnt instructions
can be created at each shared atomic operation.
This mostly reimplements LLVMBuildAtomicRMW and LLVMBuildAtomicCmpXchg
to allow for more sync scopes and uses the new functions in ac->nir with
the "workgroup-one-as" or "workgroup" sync scopes.
F1 2017 (4K, Ultra High settings, TAA), avg FPS : 59 -> 59.67 (+1.14%)
Strange Brigade (4K, ~highest settings), avg FPS : 51.5 -> 51.6 (+0.19%)
RotTR/mountain (4K, VeryHigh settings, FXAA), avg FPS : 57.2 -> 57.2 (+0.0%)
RotTR/tomb (4K, VeryHigh settings, FXAA), avg FPS : 42.5 -> 43.0 (+1.17%)
RotTR/valley (4K, VeryHigh settings, FXAA), avg FPS : 40.7 -> 41.6 (+2.21%)
Warhammer II/fallen, avg FPS : 31.63 -> 31.83 (+0.63%)
Warhammer II/skaven, avg FPS : 37.77 -> 38.07 (+0.79%)
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e91ee763c378d03883eb88cf0eadd8aa916f7878
Author: Hal Gentz <zegentzy at protonmail.com>
Date: Sun Mar 24 16:52:39 2019 -0600
glx: Fix synthetic error generation in __glXSendError
To quote Uli Schlachter, who understands this stuff more than I do:
> The function __glXSendError() in mesa's src/glx/glx_error.c invents an X11
> protocol error out of thin air. For the sequence number it uses dpy->request.
> This is the sequence number of the last request that was sent. _XError() will
> then update dpy->last_request_read based on the sequence number of the error
> that just "came in".
>
> If now another something comes in with a sequence number less than
> dpy->last_request_read, since sequence numbers are monotonically increasing,
> widen() will incorrectly add 1<<32 to the sequence number and things might go
> downhill afterwards.
`__glXSendErrorForXcb` was also patched, as that's the function that
`glXCreateContextAttribsARB` actually uses.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99781
Cc: mesa-stable at lists.freedesktop.org
Fixes: ad503c41 'apple: Initial import of libGL for OSX from AppleSGLX svn repository'
Reviewed-by: Adam Jackson <ajax at redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Hal Gentz <zegentzy at protonmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9628631a380ff24630bf97b982df07b4e7e2a79f
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Sat Apr 27 11:35:32 2019 +0800
Revert "anv: limit URB reconfigurations when using blorp"
In commit 0d46e404 ("anv: limit URB reconfigurations when using
blorp") we tried to limit the number of URB reconfiguration by
checking if the last allocation is large enough to fit the blorp
dispatch.
We used the last bound pipeline to compare the allocation. The problem
with this is that the pipeline is bound but its commands might not
have been emitted into the command buffer yet.
Let's just revert commit 0d46e404677264bfb12ada15290e39c10a5eb455
since it didn't seem to yield any performance improvement.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 0d46e404 ("anv: limit URB reconfigurations when using blorp")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110535
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc5b8a938a4064c26bd9cd034ad2cafedb04ee9a
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Thu Mar 7 13:21:50 2019 +0100
mesa/st: remove always-false state
This code is essentially dead now.
Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=be110ba2e4d5f8e5c71294d29dc991f4b6600e79
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 12:18:28 2019 +0100
mesa/st: accept NULL and empty buffer objects
It's prefectly legal and well-defined to render using a non-existing
or empty buffer object. The data coming out of the buffer object isn't
well defined unless we have the robustness flag set on the context, but
that's a different matter, and up to the shader hardware; it's the same
as out-of-bounds reads.
Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef13691e0c07d909a4f14280ca4fefbd79a9865b
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 13:28:51 2019 +0100
swr: support NULL-resources
It's legal for a buffer-object to have a NULL-resource, but let's just
skip over it, as there's nothing to do.
This patch switches the order of the conditionals in swr_update_derived,
so the logic becomes a bit more straight forward:
if (is_user_buffer)
...
else if (resource)
...
else
...
...instead of this:
if (!is_user_buffer)
if (resource)
...
else
...
else
...
Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Reviewed-by: Alok Hota <alok.hota at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=04b0c6e9df718ff0f4d9f74c2a7142de44b0eb97
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 13:28:42 2019 +0100
nouveau: support NULL-resources
It's legal for a buffer-object to have a NULL-resource, but let's just
skip over it, as there's nothing to do.
Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Acked-by: Karol Herbst <kherbst at redhat.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a11945d179b2779b24f9727b55e0a70f003f359d
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 13:28:24 2019 +0100
i915: support NULL-resources
It's legal for a buffer-object to have a NULL-resource, but let's just
skip over it, as there's nothing to do.
Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8e8204b18697e8f45643abdd5b32b6c8f3659ac
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 13:29:35 2019 +0100
gallium/u_vbuf: support NULL-resources
It's legal for a buffer-object to have a NULL-resource, but let's just
skip over it, as there's nothing to do.
Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0607ceb655d594bbc9b3240fb66be217acb36b8a
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Tue Dec 4 13:52:25 2018 +0100
mesa/st: remove impossible error-check
st_setup_current never sets this flag, and it's already checked against
right before. So let's remove this pointless check.
Signed-off-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c81fbb42d94293e78e9c767bb00ad22855f9e0b0
Author: Andres Gomez <agomez at igalia.com>
Date: Wed Jan 30 15:58:42 2019 +0200
glsl/linker: check for xfb_offset aliasing
From page 76 (page 80 of the PDF) of the GLSL 4.60 v.5 spec:
" No aliasing in output buffers is allowed: It is a compile-time or
link-time error to specify variables with overlapping transform
feedback offsets."
Currently, this is expected to fail, but it succeeds:
"
...
layout (xfb_offset = 0) out vec2 a;
layout (xfb_offset = 0) out vec4 b;
...
"
Fixes the following piglit test:
tests/spec/arb_enhanced_layouts/compiler/transform-feedback-layout-qualifiers/xfb_offset/invalid-overlap.vert
Fixes the following test:
KHR-GL44.enhanced_layouts.xfb_output_overlapping
v2:
- Use a data structure to track the used components instead of a
nested loop (Ilia).
v3:
- Take the BITSET_WORD array out from the
gl_transform_feedback_buffer struct and make it local to the
validation process (Timothy).
- Do not use a nested scope for the validation (Timothy).
v4:
- Add reference to the fixed piglit test in the commit log.
- Add reference to the fixed VK-GL-CTS test in the commit
log (Tapani).
- Empty initialize the BITSET_WORD pointers array (Tapani).
Cc: Timothy Arceri <tarceri at itsqueeze.com>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=812288bf0f65c360fd93803d14f1c74754835535
Author: Patrick Lerda <patrick9876 at free.fr>
Date: Mon Apr 29 10:43:51 2019 +0200
lima/ppir: fix pointer referenced after a free
Issue detected by valgrind.
Fixes: 92d7ca4b1cd ("gallium: add lima driver")
Signed-off-by: Patrick Lerda <patrick9876 at free.fr>
Reviewed-by: Qiang Yu <yuq825 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb953de96c769618db649b0bb735a5cce3934460
Author: Eleni Maria Stea <estea at igalia.com>
Date: Mon Apr 29 09:00:17 2019 +0200
radv: consider MESA_VK_VERSION_OVERRIDE when setting the api version
Before setting the physical device API version, we should check if the
MESA_VK_VERSION_OVERRIDE environment variable is set and take it into
account.
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9dcf90d7ba966cba904266209087a87ea9c018b9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Apr 3 14:24:31 2019 -0700
intel/fs: Don't emit empty ELSE blocks.
While we can clean this up later, it's trivial to not generate the
stupid code in the first place, which saves some optimization work.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b44b27dbe994a39d511211dcce1bb8367b0d066
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Apr 8 11:22:20 2019 -0700
nir: Add a new nir_cf_list_is_empty_block() helper.
Helper and name suggested by Eric Anholt.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08dc93c67c7d599a09cf353d50a3f0cf72f76135
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Apr 8 11:10:08 2019 -0700
glsl/list: Add an exec_list_is_singular() helper.
Similar to list_is_singular() in util/list.h.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=376c3e8f87ab0b9bce5182da60c59832f7c1c138
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Apr 12 12:52:43 2019 +0300
anv: expose VK_EXT_queue_family_foreign on Android
VK_ANDROID_external_memory_android_hardware_buffer requires this
extension. It is safe to enable it since currently aux usage is
disabled for ahw buffers.
Fixes following dEQP extension dependency test on Android:
dEQP-VK.api.info.device#extensions
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c960323a81456b05570ed9647f19207e7733aa11
Author: Andreas Baierl <ichgeh at imkreisrum.de>
Date: Fri Apr 26 15:06:13 2019 +0200
lima/ppir: Add gl_FragCoord handling
Treat gl_FragCoord variable as a system value and lower the w component
with a nir pass.
Add the necessary bits for correct codegen.
Signed-off-by: Andreas Baierl <ichgeh at imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b82de2b4d702789620f84c70577aa3e106d6ae4f
Author: Andreas Baierl <ichgeh at imkreisrum.de>
Date: Fri Apr 26 15:01:43 2019 +0200
nir: add rcp(w) lowering for gl_FragCoord
On some hardware (e.g. Mali400) the shader needs to apply some
transformations for correct gl_FragCoord handling. The lowering
actions look like the following in pseudocode:
gl_FragCoord.xyz = gl_FragCoord_orig.xyz
gl_FragCoord.w = 1.0 / gl_FragCoord_orig.w
Add this lowering as a nir pass in preparation for using it in the driver.
Signed-off-by: Andreas Baierl <ichgeh at imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7050eccd77f6f435ab4c8ab4a31706e42b53817b
Author: Romain Failliot <romain.failliot at foolstep.com>
Date: Sat Apr 27 17:02:21 2019 -0400
docs: changed "Done" to "DONE" in features.txt
Mesamatrix.net expects uppercase.
Acked-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec65e1b763edadbc4f7bddd122b1fbbdb2c5bfd0
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sun Apr 28 21:39:20 2019 +0000
panfrost: Workaround -bshadow regression
I have *no* idea what's happening here, but let's not regress an app
that used to work in the mean time while we're figuring it out..
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3978614d8818ece6e1e252490f4bcab670db806a
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sun Apr 28 15:46:47 2019 +0000
panfrost/midgard: Safety check immediate precision degradations
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ebf1047a4fcb8c6703c5d3f8bd1d7e47a478e46
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sun Apr 28 15:21:34 2019 +0000
panfrost: Use fp32 (not fp16) varyings
In a perfect world, we'd use fp16 varyings for mediump and fp32 for
highp, allowing us to get a performance win without sacrificing
conformance. Unfortunately, we're not there (yet), so it's better we
assume always fp32 than always fp16 to avoid artefacts / breaking a lot
of deqp.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a81267f228575335446ec2a2e6ca64a3df7dba5e
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sun Apr 28 04:58:43 2019 +0000
panfrost/midgard: imov workaround
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53d6e11393744423b7cbf29459b81bde80ba1516
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sun Apr 28 04:38:01 2019 +0000
panfrost/midgard: Fix tex propogation
Unbreaks mpv.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=68a1508dc9dfb283dce18921273bf218086eb2ce
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sun Apr 28 03:47:57 2019 +0000
panfrost/midgard: Fix regressions in -bjellyfish
Two fixes here, one is that we tried to copyprop non-strictly-SSA values
which was bound to fly in our face. The other was peeling back the imov
workaround.. Turns out we still need that. More research is needed
still, but let's not regress real apps.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdaa23b32be9f1631da795b59dae7ef5e5183ef5
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sat Apr 27 23:49:52 2019 +0000
panfrost/midgard: Only copyprop without an outmod
With an outmod, we would need to propagate that through, which is for
future work.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3d6a3dfc43871db34e68d6209f6f47917828455
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sat Apr 27 23:46:38 2019 +0000
Revert "panfrost/midgard: Extend copy propagation pass"
Fixes: commit b53b4573c3f0571253672e44ce7d6310d9f987bf.
Optimization gone wrong. In the future, we should try this again (it's a
net win if implemented right), but at the moment this just regresses.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=07745f94948874c875dac924e055a11ee96beb5b
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Apr 27 12:07:51 2019 +0200
radv: add missing VEGA20 chip in radv_get_device_name()
Otherwise it returns "AMD RADV unknown".
Cc: 19.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bd4cb920e9c0b431df3ab2f5878b2b24182fd00
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Apr 27 00:24:05 2019 -0700
iris: Fix zeroing of transform feedback offsets in strange cases.
Some of the dEQP.functional.transform_feedback tests end up doing
the following sequence of operations:
1. BeginTransformFeedback
2. PauseTransformFeedback
3. Draw
4. ResumeTransformFeedback
At step 1, we'd pack 3DSTATE_SO_BUFFER commands saying to zero the
SO_WRITE_OFFSET registers. At step 2, we disable streamout, so step 3
doesn't bother emitting those commands. Then, step 4 re-packs new
3DSTATE_SO_BUFFER commands with offset = 0xFFFFFFFF, saying to continue
appending at the existing offset. This loads the value from the BO as
the offsets - but we never actually zeroed it.
So, just maintain a flag saying "we actually emitted the commands",
and stomp offset back to zero until we emit some.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=edb04953c8b8520108f333b1e289f18719a7d597
Author: Eric Anholt <eric at anholt.net>
Date: Fri Oct 26 18:19:37 2018 -0700
vc4: Fall back to renderonly if the vc4 driver doesn't have v3d.
I have a platform with vc4 display but V3D 4.x. We can fall back on
kmsro's probing to bring up the v3d gallium driver.
Acked-by: Rob Clark <robdclark at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e069832a05ebd5948d3ef95d3b5028156c829b3
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 3 15:40:22 2019 -0700
kmsro: Add support for V3D.
Like vc4, we expect to have SOCs with various displays that have a single
V3D instance for rendering.
v2: Add v3d to the list of drivers that make enabling kmsro valid.
Acked-by: Rob Clark <robdclark at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8a0e5c03cab8dc0e73d761fdf44874f7f45be55
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 25 19:42:25 2019 -0400
radeonsi: don't ignore PIPE_FLUSH_ASYNC
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb0611df3d406804da738d599a22da99aa382682
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 25 12:58:12 2019 -0700
v3d: Fix detection of TMU write sequences in register spilling.
We can't use the QPU functions to detect this until register allocation is
done and we've moved inst->dst into inst->qpu.
Fixes bad TMU sequences from register spilling in
KHR-GLES31.core.compute_shader.shared-max.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18894a5e5a55e110aa0b2a64d5446c4ffcef1365
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 25 12:29:55 2019 -0700
v3d: Fix detection of the last ldtmu before a new TMU op.
We were looking at the start instruction, instead of scanning through the
list of following instructions to find any more ldtmus.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=575caab895d75e80d790357d68943cc78b877ea2
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 25 11:30:39 2019 -0700
v3d: Re-add support for memory_barrier_shared.
Looks like I lost it in a rebase conflict resolution. We'd hit the
unknown intrinsic assertion in
KHR-GLES31.core.compute_shader.shared-struct.
Fixes: 6b1c65982509 ("v3d: Add Compute Shader compilation support.")
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=971a13d8050a37a19060f560833b63609c0e70d6
Author: Eric Anholt <eric at anholt.net>
Date: Tue Apr 23 11:10:56 2019 -0700
Revert "v3d: Disable PIPE_CAP_BLIT_BASED_TEXTURE_TRANSFER."
This reverts commit ccce9409470c1053c40c822d759b9bd417062bc0, leaving a
note as to why we had to (corruption in chromium, breaking some GLES3.1
tests).
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=49071b2e3ff2a34b817483d38d286c04c8fa39cf
Author: Eric Anholt <eric at anholt.net>
Date: Mon Apr 22 11:04:32 2019 -0700
v3d: Don't try to update the shadow texture for separate stencil.
There are two cases where v3d's sampler view's resource doesn't match the
base's: shadow textures for sampling from raster, and pointing at the
separate depth texture for z32f_s8x24. We only want to update shadow for
the first case.
Fixes
dEQP-GLES31.functional.stencil_texturing.render.depth32f_stencil8_draw
when run after the previous testcase.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4358904c06838138b17e7e81b55d3a04d50dde1e
Author: Eric Anholt <eric at anholt.net>
Date: Mon Apr 22 10:40:47 2019 -0700
v3d: Add a note about i/o indirection for future performance work.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c74d0e7f6278b885b6b195b8e8daef36c775d4ec
Author: Eric Anholt <eric at anholt.net>
Date: Fri Apr 19 14:28:40 2019 -0700
vc4: Use _mesa_hash_table_remove_key() where appropriate.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8486c2ad71a20874043419a6156e1bd4bbb4c83
Author: Eric Anholt <eric at anholt.net>
Date: Fri Apr 19 14:26:42 2019 -0700
v3d: Use _mesa_hash_table_remove_key() where appropriate.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=24587ae8ae979de759cff697df9b6652eb75e3da
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 25 11:23:55 2019 -0700
v3d: Assert that we do request the normal texturing return data.
An unused tex should be DCEed, but if it wasn't we'd run into trouble with
not doing a TMUWT.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=42210a4351fbb53a44eb49f31a12e86d7a84ffa4
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 24 11:26:34 2019 -0700
v3d: Apply the GFXH-930 workaround to the case where the VS loads attrs.
We were emitting a dummy load for when the VS doesn't load any attributes,
but we also need to emit a dummy load for when the render VS loads
attributes but the binner VS doesn't. Fixes simulator assertion failures
and GPU hangs on KHR-GLES31.core.texture_gather.\*
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=448fc3ea427ed0edebe2ab5f81c585a5273bafd3
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 24 17:25:08 2019 -0700
v3d: Fill in the ignored segment size fields to appease new simulator.
We are assured that the input segment size field is ignored for
!separate_segs mode, and now the simulator wants an in-range value set
regardless of whether it's functionally ignored or not.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=af06963d245557d62d78192a7a78b5d610bbf0e9
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Apr 23 14:31:44 2019 +0300
glsl: use empty brace initializer
fixes following warning with clang:
warning: suggest braces around initialization of subobject
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg at google.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=976004d0e70757a0b57707e419677acb71c054c5
Author: coypu <coypu at sdf.org>
Date: Sun Apr 7 23:31:37 2019 +0300
gbm: don't return void
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a7f182dac0b8f29f83a2eca02d29f10e8b23244
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Apr 23 14:35:17 2019 +0300
nir: use braces around subobject in initializer
Used same syntax as elsewhere with Mesa sources, verified result
against MSVC with godbolt.org.
fixes following warning with clang:
warning: suggest braces around initialization of subobject
v2: empty braces -> braces around subobject (Caio, Kristian)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg at google.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7c70bb2a1cee01e11b4b32df8213ac653eb7959
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Fri Apr 26 11:37:36 2019 -0700
freedreno/drm: Quiet pointer to u64 conversion warning
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8bfb34fd0adf23fdb73cf5e4253b42cb2da58188
Author: Alok Hota <alok.hota at intel.com>
Date: Mon Oct 22 11:53:38 2018 -0500
swr/rast: enforce use of tile offsets
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e49963212fb85e4fb83c3d4003907e232f151bd
Author: Alok Hota <alok.hota at intel.com>
Date: Tue Jun 19 17:22:32 2018 -0500
swr/rast: AVX512 support compiled in by default
- Emulation of AVX512 built into SIMDLIB
- Remove associated macros
- Remove knobs controlling AVX512 and let emulation handle it
- Refactor variable names for SIMD16
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0bf1df2bb6e2311c532734c4cb6a096389e511bf
Author: Alok Hota <alok.hota at intel.com>
Date: Thu Jun 14 12:30:56 2018 -0500
swr/rast: Remove deprecated 4x2 backend code
- Use 8x2 tiling by default
- Remove associated macros
- Use SIMDLIB emulation for SIMD16 on SIMD8 hardware
- Remove code rot in Load/StoreTile
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
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