Mesa (master): intel/compiler: force simd8 when dual src blending on gen8

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Module: Mesa
Branch: master
Commit: 32ebd4207ad9411bc790b5e2c7e8d2a4f21c3d67
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=32ebd4207ad9411bc790b5e2c7e8d2a4f21c3d67

Author: Tapani Pälli <tapani.palli at intel.com>
Date:   Mon Dec  2 16:54:30 2019 +0200

intel/compiler: force simd8 when dual src blending on gen8

Patch introduces option to force simd8 and uses it as a workaround for
dual source blending issues seen with skqp (skia testsuite) on gen8.

Fixes following Piglit test on gen8 platforms:
   arb_blend_func_extended-dual-src-blending-issue-1917

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1917
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
c: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

---

 src/intel/compiler/brw_fs.cpp | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 52a54fecdaa..b19f8fab3a9 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -8274,6 +8274,16 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
       prog_data->reg_blocks_8 = brw_register_blocks(v8.grf_used);
    }
 
+   /* Limit dispatch width to simd8 with dual source blending on gen8.
+    * See: https://gitlab.freedesktop.org/mesa/mesa/issues/1917
+    */
+   if (devinfo->gen == 8 && prog_data->dual_src_blend &&
+       !(INTEL_DEBUG & DEBUG_NO8)) {
+      assert(!use_rep_send);
+      v8.limit_dispatch_width(8, "gen8 workaround: "
+                              "using SIMD8 when dual src blending.\n");
+   }
+
    if (v8.max_dispatch_width >= 16 &&
        likely(!(INTEL_DEBUG & DEBUG_NO16) || use_rep_send)) {
       /* Try a SIMD16 compile */