Mesa (19.0): 21 new commits
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Tue Feb 19 22:28:16 UTC 2019
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e7833ad916c493969d00871cdf56db4407b80eb
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Tue Feb 19 11:15:18 2019 -0800
Version: update to 19.0-rc5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a2e4b02ca6f0bf4b198b10a2752fb33064f44ab
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Feb 14 09:02:31 2019 +0200
mesa: return NULL if we exceed MaxColorAttachments in get_fb_attachment
This fixes invalid access to Attachment array which would occur if caller
would exceed MaxColorAttachments. In practice this should not ever happen
because DiscardFramebufferEXT specifies only GL_COLOR_ATTACHMENT0 to be
valid and InvalidateFramebuffer will error out before but this should
make coverity happy.
v2: const, remove _EXT (Ian)
CID: 1442559
Fixes: 0c42b5f3cb9 "mesa: wire up InvalidateFramebuffer"
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
(cherry picked from commit 9762a9f89380a8070654a80e73d927297c29da35)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7fc61d15b5db5340dfe3eca633c8fc86d81b0d4
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Dec 6 12:11:00 2018 +0000
radv: ensure export arguments are always float
So that the signature is correct and consistent, the inputs to a export
intrinsic should always be 32-bit floats.
This and the previous commit fixes a large amount crashes from
dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_*
tests
Fixes: b722b29f10d ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 0ca550e01ac55c67c2deef50f5cb750a0181352b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b093b567f8aa0dc24530006cc0aeffa90ecd3ab
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Dec 6 12:10:41 2018 +0000
radv: bitcast 16-bit outputs to integers
16-bit outputs are stored as 16-bit floats in the outputs array, so they
have to be bitcast.
Fixes: b722b29f10d ('radv: add support for 16bit input/output')
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 64065aa504c4872a15f7b0894b6037a6b2bcae65)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d73e48b63ff6011b39da7c3be139f1e4bff9dd76
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 14 09:42:38 2019 -0800
v3d: Fix the check for "is the last thrsw inside control flow"
The execute.file check used to be good enough, until I stopped setting up
the execute mask for uniform ifs.
No known tests fixed, noticed while doing a refactor.
Fixes: 080506057310 ("v3d: Handle dynamically uniform IF statements with uniform control flow.")
(cherry picked from commit 441294962cd65d44febdbe9ef0b0d99b5d27cec8)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba24ca67f6d5532037c6c4a4528cf22a05872109
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 12 14:39:40 2019 -0800
v3d: Use the early_fragment_tests flag for the shader's disable-EZ field.
Apparently we need disable-EZ flagged, not just "does Z writes".
Fixes
dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo
on 7278, even though it passed in simulation.
Signed-off-by: Eric Anholt <eric at anholt.net>
Fixes: 051a41d3d56e ("v3d: Add support for the early_fragment_tests flag.")
(cherry picked from commit cd5e0b272919a654079620adecd2abe24ff51233)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=110500cc8ab5dfc2b0d5c464155f85b1bccba779
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Feb 18 17:42:10 2019 +0100
radv: fix writing the alpha channel of MRT0 when alpha coverage is enabled
This version is better and safer.
Cc: 18.3 19.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 47616810ed7cfce21d239391131ad9a5ef558b52)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b9f6ebfbbb792e6b592044a1577a3e3fae6e50c
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Feb 15 18:02:52 2019 +0100
radv: write the alpha channel of MRT0 when alpha coverage is enabled
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597
Cc: 18.3 19.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 0d8f09629377da9cf48ab4315574d69fdef5369d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69ebf4569ae0d2c7d9b1dc04de145329a1684727
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Feb 15 14:52:20 2019 -0800
nir: Don't reassociate add/mul chains containing only constants
The idea here is to reassociate a * (b * c) into (a * c) * b, when
b is a non-constant value, but a and c are constants, allowing them
to be combined.
But nothing was enforcing that 'b' must be non-constant, which meant
that running opt_algebraic in a loop would never terminate if the IR
contained non-folded constant expressions like 256 * 0.5 * 2. Normally,
we call constant folding in such a loop too, but IMO it's better for
nir_opt_algebraic to be robust and not rely on that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109581
Fixes: 32e266a9a58 i965: Compile fp64 funcs only if we do not have 64-bit hardware support
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
(cherry picked from commit 535251487ba56c4fd98465c4682881c2b9734242)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=385b7362385b4f648508768c20b057eed2022409
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Feb 11 13:41:32 2019 -0800
intel/compiler/test: Add unit test for mismatched signedness comparison
v2 (idr): Move adding the test to after adding the fix. Reordering the
two commits prevents possible headaches for git-bisect with scripts that
always do 'ninja check'.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109404
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
(cherry picked from commit ac21dd4aee450b2a4bc63adb05356b07abba2ff6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cf1a40f9a33517d9fc1bb4439528af49699661b
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Feb 11 16:02:15 2019 -0800
intel/compiler: Avoid propagating inequality cmods if types are different
v2: Fix silly bug in logic. s/||/&&/
All but one of the affected shaders is in an Unreal4 demo. The other is
in Tomb Raider. All of the cases that Ian investigated appear to be
sequences like the following
if (int(uint(some_float)) < 0) /* other relations too */
...
At least in Tomb Raider, it's not obvious that this sequence came from
the original shader.
In some of the Unreal demos, the shader contains code like
if (int(uint(textureLod(...))) > 0)
...
which explicitly generates the offending sequence.
All Gen6+ platforms had similar results (Skylake shown):
total instructions in shared programs: 15437170 -> 15437187 (<.01%)
instructions in affected programs: 4492 -> 4509 (0.38%)
helped: 0
HURT: 17
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.05% max: 0.73% x̄: 0.66% x̃: 0.73%
95% mean confidence interval for instructions value: 1.00 1.00
95% mean confidence interval for instructions %-change: 0.57% 0.75%
Instructions are HURT.
total cycles in shared programs: 383007996 -> 383007992 (<.01%)
cycles in affected programs: 20542 -> 20538 (-0.02%)
helped: 6
HURT: 7
helped stats (abs) min: 2 max: 6 x̄: 5.33 x̃: 6
helped stats (rel) min: 0.11% max: 0.36% x̄: 0.32% x̃: 0.36%
HURT stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
HURT stats (rel) min: 0.27% max: 0.27% x̄: 0.27% x̃: 0.27%
95% mean confidence interval for cycles value: -3.30 2.69
95% mean confidence interval for cycles %-change: -0.19% 0.19%
Inconclusive result (value mean confidence interval includes 0).
No changes on Iron Lake or GM45.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109404
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Tested-by: nagrigoriadis at gmail.com
Tested-by: Danylo Piliaiev <danylo.piliaiev at gmail.com>
(cherry picked from commit 2dff9a66b629834bffad47e7a9025e0f1de5ffc3)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=81e053b7578e540588e897b4d7670d0dfd8b0ab8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 11 22:39:45 2019 -0600
intel/fs: Bail in optimize_extract_to_float if we have modifiers
This fixes a bug in runscape where we were optimizing x >> 16 to an
extract and then negating and converting to float. The NIR to fs pass
was dropping the negate on the floor breaking a geometry shader and
causing it to render nothing.
Fixes: 1f862e923cb "i965/fs: Optimize float conversions of byte/word..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109601
Tested-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit 367b0ede4d9115aba772d6e46ec73642761f7ff6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f30fb27665d8341b7c71f601dafe091856b97874
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Feb 13 22:32:25 2019 -0500
swr: set PIPE_CAP_MAX_VARYINGS correctly
Unfortunately swr was missed in the original commit. The number of
varyings should generally match up to what's reported as the shader
caps for fragment inputs.
Fixes: 6010d7b8e8be (gallium: add PIPE_CAP_MAX_VARYINGS)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Alok Hota <alok.hota at intel.com>
Cc: 19.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 8c859367df95b74e7596f7fefffbdbf08bb8f8c7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=103928528883dde66e48bc68f1cd740f65de69a7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 14 08:55:37 2019 -0800
anv: Put MOCS in the correct location
My patch to switch from struct-based MOCS to numeric MOCS accidentally
divided all MOCS entries by 2 in the Vulkan driver.
MOCS on Gen9+ is just an array index into a table. But in the hardware
packets, the index starts at bit 1. So we need to shift it.
Fixes: 0b44644ca68 (genxml: Consistently use a numeric "MOCS" field)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 39aee57523a02552e7eae7df5da488e535aeb1eb)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59812ac38dfeb6a1e92d0c333aeb4f1ea0f89bd9
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 13 15:01:16 2019 -0800
spirv: Add missing break
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Fixes: c6465fec0c5 ("spirv: add SpvCapabilityInt64Atomics")
CID: 1442555
(cherry picked from commit 9a918050e0886d8c6d6adc0c687ffd30d8f70b40)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c19ce6e5e26b44e13376fba1a5ea4fd60ad9dd5b
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Feb 13 09:26:16 2019 -0800
meson: Add dependency on genxml to anvil
Currently the Intel "anvil" driver races with the generation of genxml
files, while i965 has an explicit dependency. This patch adds the same
dependency to anvil.
Fixes: d1992255bb29054fa51763376d125183a9f602f
("meson: Add build Intel "anv" vulkan driver")
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
(cherry picked from commit 279060cd32dd673c6a5bf302ceac852f51a6c17c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eba57c29b09ef8d6770d2ba71d22a3e1cca08146
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Feb 12 09:50:15 2019 +0100
radv: always export gl_SampleMask when the fragment shader uses it
For some reasons, this breaks trees rendering in Project Cars.
Fixes: 85010585cde ("radv: only enable gl_SampleMask if MSAA is enabled too")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109401
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 334da034d8d91ca5a0a1bff8deaefd8ca762c42e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e304007d87ad99968dfded7048a81c947ce4ffdc
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Feb 13 18:51:23 2019 +0100
radv/winsys: fix BO list creation when RADV_DEBUG=allbos is set
Fixes: 50fd253bd6e ("radv/winsys: Add priority handling during submit.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 5e18000d1b070ecf627138b7bff47ff8fef81576)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4419fdba50856b5963f2728d819433130b30888
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Tue Feb 12 14:03:21 2019 -0800
get-pick-list: Add --pretty=medium to the arguments for Cc patches
Because none of them have been picked up for 19.0 due to this bug
being reintroduced.
v2: - Fix fixes tags
Fixes: e6b3a3b2014413366110f6deeced8095e7262b1d
("bin/get-pick-list.sh: handle "typod" usecase.")
Fixes: fac10169bbad2da918ef07a62c01e0b321508cfe
("bin/get-pick-list.sh: prefix output with "[stable] "")
Reviewed-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit aff52dd2c61eb8d1b03cebbcca7e070ffa48afdf)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ac15d9e4248ddafba8189e5dfcacddc1af367e2
Author: Karol Herbst <kherbst at redhat.com>
Date: Tue Feb 12 20:59:35 2019 +0100
nir/opt_if: don't mark progress if nothing changes
if we have something like this:
loop {
...
if x {
break;
} else {
continue;
}
}
opt_if_loop_last_continue returns true marking progress allthough nothing
changes.
Fixes: 5921a19d4b0c6 "nir: add if opt opt_if_loop_last_continue()"
Signed-off-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 7e08f22a72cfc379902feeca3673db6aa344f782)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b484511104c5bddfd552cb83b1c7ee600004000
Author: Oscar Blumberg <carnaval at 12-10e.me>
Date: Tue Feb 12 21:52:51 2019 +0100
radeonsi: Fix guardband computation for large render targets
Stop using 12.12 quantization for viewports that are not contained in
the lower 4k corner of the render target as the hardware needs to keep
both absolute and relative coordinates representable.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
Cc: 18.3 19.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 3c540e0a748844258e77254fc4f864f3b875fe18)
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