Mesa (master): virgl: don't flush an empty range

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: ca66457b0516ef8af5ef17c54460ab8d9aefc5fa
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca66457b0516ef8af5ef17c54460ab8d9aefc5fa

Author: Gurchetan Singh <gurchetansingh at chromium.org>
Date:   Sat Dec 29 00:07:25 2018 +0100

virgl: don't flush an empty range

Otherwise, the gl-1.0-long-dlist Piglit test crashes.

Fixes: db7757 ("virgl: modify how we handle GL_MAP_FLUSH_EXPLICIT_BIT")
Reported by airlied@

v2: Exit on any invalid range (Erik)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109190
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Tested-by: Jakob Bornecrantz <jakob at collabora.com>

---

 src/gallium/drivers/virgl/virgl_buffer.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/virgl/virgl_buffer.c b/src/gallium/drivers/virgl/virgl_buffer.c
index cee26da41b..4d30c6c340 100644
--- a/src/gallium/drivers/virgl/virgl_buffer.c
+++ b/src/gallium/drivers/virgl/virgl_buffer.c
@@ -83,6 +83,9 @@ static void virgl_buffer_transfer_unmap(struct pipe_context *ctx,
    if (trans->base.usage & PIPE_TRANSFER_WRITE) {
       struct virgl_screen *vs = virgl_screen(ctx->screen);
       if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
+         if (trans->range.end <= trans->range.start)
+            goto out;
+
          transfer->box.x += trans->range.start;
          transfer->box.width = trans->range.end - trans->range.start;
          trans->offset = transfer->box.x;
@@ -96,6 +99,7 @@ static void virgl_buffer_transfer_unmap(struct pipe_context *ctx,
 
    }
 
+out:
    virgl_resource_destroy_transfer(vctx, trans);
 }