Mesa (master): radeonsi: move PKT3_WRITE_DATA generation into a helper function
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Tue Jan 22 17:15:04 UTC 2019
Module: Mesa
Branch: master
Commit: 4d5f8f39f3b34e308ec8a763cbaba16ced8b713c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d5f8f39f3b34e308ec8a763cbaba16ced8b713c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jan 17 15:07:03 2019 -0500
radeonsi: move PKT3_WRITE_DATA generation into a helper function
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
---
src/gallium/drivers/radeonsi/si_cp_dma.c | 25 +++++++++++++++++++++++++
src/gallium/drivers/radeonsi/si_descriptors.c | 10 ++--------
src/gallium/drivers/radeonsi/si_fence.c | 21 ++++++++-------------
src/gallium/drivers/radeonsi/si_pipe.c | 13 ++-----------
src/gallium/drivers/radeonsi/si_pipe.h | 3 +++
src/gallium/drivers/radeonsi/si_state_draw.c | 12 +++---------
6 files changed, 43 insertions(+), 41 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 80673f3f5f..59360c0d4a 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -581,3 +581,28 @@ void si_test_gds(struct si_context *sctx)
pipe_resource_reference(&dst, NULL);
exit(0);
}
+
+void si_cp_write_data(struct si_context *sctx, struct r600_resource *buf,
+ unsigned offset, unsigned size, unsigned dst_sel,
+ unsigned engine, const void *data)
+{
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
+
+ assert(offset % 4 == 0);
+ assert(size % 4 == 0);
+
+ if (sctx->chip_class == SI && dst_sel == V_370_MEM)
+ dst_sel = V_370_MEM_GRBM;
+
+ radeon_add_to_buffer_list(sctx, cs, buf,
+ RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
+ uint64_t va = buf->gpu_address + offset;
+
+ radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + size/4, 0));
+ radeon_emit(cs, S_370_DST_SEL(dst_sel) |
+ S_370_WR_CONFIRM(1) |
+ S_370_ENGINE_SEL(engine));
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+ radeon_emit_array(cs, (const uint32_t*)data, size/4);
+}
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 71ae00c53c..ca62848296 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1821,7 +1821,6 @@ static void si_upload_bindless_descriptor(struct si_context *sctx,
unsigned num_dwords)
{
struct si_descriptors *desc = &sctx->bindless_descriptors;
- struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned desc_slot_offset = desc_slot * 16;
uint32_t *data;
uint64_t va;
@@ -1829,13 +1828,8 @@ static void si_upload_bindless_descriptor(struct si_context *sctx,
data = desc->list + desc_slot_offset;
va = desc->gpu_address + desc_slot_offset * 4;
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + num_dwords, 0));
- radeon_emit(cs, S_370_DST_SEL(V_370_TC_L2) |
- S_370_WR_CONFIRM(1) |
- S_370_ENGINE_SEL(V_370_ME));
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
- radeon_emit_array(cs, data, num_dwords);
+ si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address,
+ num_dwords * 4, V_370_TC_L2, V_370_ME, data);
}
static void si_upload_bindless_descriptors(struct si_context *sctx)
diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index 46d0289c90..84bf4d10c2 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -259,21 +259,16 @@ static void si_fine_fence_set(struct si_context *ctx,
*fence_ptr = 0;
- uint64_t fence_va = fine->buf->gpu_address + fine->offset;
-
- radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
- RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
- struct radeon_cmdbuf *cs = ctx->gfx_cs;
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
- radeon_emit(cs, S_370_DST_SEL(ctx->chip_class >= CIK ? V_370_MEM
- : V_370_MEM_GRBM) |
- S_370_WR_CONFIRM(1) |
- S_370_ENGINE_SEL(V_370_PFP));
- radeon_emit(cs, fence_va);
- radeon_emit(cs, fence_va >> 32);
- radeon_emit(cs, 0x80000000);
+ uint32_t value = 0x80000000;
+
+ si_cp_write_data(ctx, fine->buf, fine->offset, 4,
+ V_370_MEM, V_370_PFP, &value);
} else if (flags & PIPE_FLUSH_BOTTOM_OF_PIPE) {
+ uint64_t fence_va = fine->buf->gpu_address + fine->offset;
+
+ radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
+ RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
si_cp_release_mem(ctx,
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index b6953b8bd2..4edb25494e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -526,17 +526,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
goto fail;
/* Initialize the memory. */
- struct radeon_cmdbuf *cs = sctx->gfx_cs;
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
- radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM
- : V_370_MEM_GRBM) |
- S_370_WR_CONFIRM(1) |
- S_370_ENGINE_SEL(V_370_ME));
- radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
- radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
- radeon_emit(cs, sctx->wait_mem_number);
- radeon_add_to_buffer_list(sctx, cs, sctx->wait_mem_scratch,
- RADEON_USAGE_WRITE, RADEON_PRIO_FENCE);
+ si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
+ V_370_MEM, V_370_ME, &sctx->wait_mem_number);
}
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 957629e463..89a93182ed 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1176,6 +1176,9 @@ void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf
uint64_t offset, unsigned size);
void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
void si_test_gds(struct si_context *sctx);
+void si_cp_write_data(struct si_context *sctx, struct r600_resource *buf,
+ unsigned offset, unsigned size, unsigned dst_sel,
+ unsigned engine, const void *data);
/* si_debug.c */
void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 9a80bd8132..1ff74e7743 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1592,17 +1592,11 @@ si_draw_rectangle(struct blitter_context *blitter,
void si_trace_emit(struct si_context *sctx)
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
- uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
- radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
- radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM
- : V_370_MEM_GRBM) |
- S_370_WR_CONFIRM(1) |
- S_370_ENGINE_SEL(V_370_ME));
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
- radeon_emit(cs, trace_id);
+ si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
+ 0, 4, V_370_MEM, V_370_ME, &trace_id);
+
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
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