Mesa (master): radv: make sure to mark the image as compressed when clearing DCC levels

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Module: Mesa
Branch: master
Commit: cc50c85e1378c560785cf8b241ffa4cdb36f0c29
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc50c85e1378c560785cf8b241ffa4cdb36f0c29

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Jun 27 15:06:15 2019 +0200

radv: make sure to mark the image as compressed when clearing DCC levels

Found while working on DCC for arrays.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_cmd_buffer.c | 22 ++--------------------
 src/amd/vulkan/radv_meta.h       |  3 ---
 src/amd/vulkan/radv_meta_clear.c | 10 ++++++----
 3 files changed, 8 insertions(+), 27 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index dac966f1a28..1f3fdd1abd0 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4952,32 +4952,14 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
 			 const VkImageSubresourceRange *range, uint32_t value)
 {
 	struct radv_cmd_state *state = &cmd_buffer->state;
-	uint32_t level_count = radv_get_levelCount(image, range);
 	unsigned size = 0;
 
 	state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 			     RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
 
-	if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
-		/* Mipmap level aren't implemented. */
-		assert(level_count == 1);
-		state->flush_bits |= radv_clear_dcc(cmd_buffer, image,
-						    range, value);
-	} else {
-		/* Initialize the mipmap levels with DCC first. */
-		for (unsigned l = 0; l < level_count; l++) {
-			uint32_t level = range->baseMipLevel + l;
-			struct legacy_surf_level *surf_level =
-				&image->planes[0].surface.u.legacy.level[level];
-
-			if (!surf_level->dcc_fast_clear_size)
-				break;
-
-			state->flush_bits |=
-				radv_dcc_clear_level(cmd_buffer, image,
-						     level, value);
-		}
+	state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
 
+	if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
 		/* When DCC is enabled with mipmaps, some levels might not
 		 * support fast clears and we have to initialize them as "fully
 		 * expanded".
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index c3d37bb07d2..e916b788d0e 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -220,9 +220,6 @@ uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
 uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
 			struct radv_image *image,
 			const VkImageSubresourceRange *range, uint32_t value);
-uint32_t radv_dcc_clear_level(struct radv_cmd_buffer *cmd_buffer,
-			      const struct radv_image *image,
-			      uint32_t level, uint32_t value);
 uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
 			  struct radv_image *image,
 			  const VkImageSubresourceRange *range, uint32_t value);
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 091b73841f8..b0b17f4f7b3 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1367,7 +1367,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
 	return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
 }
 
-uint32_t
+static uint32_t
 radv_dcc_clear_level(struct radv_cmd_buffer *cmd_buffer,
 		     const struct radv_image *image,
 		     uint32_t level, uint32_t value)
@@ -1383,9 +1383,11 @@ radv_dcc_clear_level(struct radv_cmd_buffer *cmd_buffer,
 		const struct legacy_surf_level *surf_level =
 			&image->planes[0].surface.u.legacy.level[level];
 
-		/* If this is 0, fast clear isn't possible. */
-		assert(surf_level->dcc_fast_clear_size);
-
+		/* If dcc_fast_clear_size is 0 (which might happens for
+		 * mipmaps) the fill buffer operation below is a no-op. This
+		 * can only happen during initialization as the fast clear path
+		 * fallbacks to slow clears if one level can't be fast cleared.
+		 */
 		offset += surf_level->dcc_offset;
 		size = surf_level->dcc_fast_clear_size;
 	}