Mesa (master): radv: Add export_prim_id to the shader variant info.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 43f2f01cc89def665bd0e33f9ad689825b85e977
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=43f2f01cc89def665bd0e33f9ad689825b85e977

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Jul  2 00:41:47 2019 +0200

radv: Add export_prim_id to the shader variant info.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 2 ++
 src/amd/vulkan/radv_shader.c      | 4 ++--
 src/amd/vulkan/radv_shader.h      | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 1f86d3af6c8..a7e949a1c04 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3973,6 +3973,7 @@ ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_sha
                 shader_info->tes.ccw = nir->info.tess.ccw;
                 shader_info->tes.point_mode = nir->info.tess.point_mode;
                 shader_info->tes.as_es = options->key.tes.as_es;
+                shader_info->tes.export_prim_id = options->key.tes.export_prim_id;
                 break;
         case MESA_SHADER_TESS_CTRL:
                 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
@@ -3980,6 +3981,7 @@ ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_sha
         case MESA_SHADER_VERTEX:
                 shader_info->vs.as_es = options->key.vs.as_es;
                 shader_info->vs.as_ls = options->key.vs.as_ls;
+                shader_info->vs.export_prim_id = options->key.vs.export_prim_id;
                 break;
         default:
                 break;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 3d71ab73288..073ed39b5b8 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -501,7 +501,7 @@ radv_fill_shader_variant(struct radv_device *device,
 			assert(device->physical_device->rad_info.chip_class <= GFX8);
 			vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
 		} else {
-			bool enable_prim_id = options->key.tes.export_prim_id || info->uses_prim_id;
+			bool enable_prim_id = variant->info.tes.export_prim_id || info->uses_prim_id;
 			vgpr_comp_cnt = enable_prim_id ? 3 : 2;
 		}
 		variant->config.rsrc2 |= S_00B12C_OC_LDS_EN(1);
@@ -534,7 +534,7 @@ radv_fill_shader_variant(struct radv_device *device,
 			 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
 			 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
 			 */
-			if (options->key.vs.export_prim_id) {
+			if (variant->info.vs.export_prim_id) {
 				vgpr_comp_cnt = 2;
 			} else if (info->vs.needs_instance_id) {
 				vgpr_comp_cnt = 1;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index f6f345e1eed..66cd005e5fc 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -268,6 +268,7 @@ struct radv_shader_variant_info {
 			struct radv_es_output_info es_info;
 			bool as_es;
 			bool as_ls;
+			bool export_prim_id;
 		} vs;
 		struct {
 			unsigned num_interp;
@@ -302,6 +303,7 @@ struct radv_shader_variant_info {
 			enum gl_tess_spacing spacing;
 			bool ccw;
 			bool point_mode;
+			bool export_prim_id;
 		} tes;
 	};
 };