Mesa (master): radv/gfx10: enable vertex shaders without export parameters

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Module: Mesa
Branch: master
Commit: df062afa03c9bccbe14919600ebadc2e3fe3db58
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=df062afa03c9bccbe14919600ebadc2e3fe3db58

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Jul 12 12:17:14 2019 +0200

radv/gfx10: enable vertex shaders without export parameters

GFX10 allows this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_pipeline.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a58b0d6d006..63583a9c6d9 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3287,9 +3287,17 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
 	bool misc_vec_ena = outinfo->writes_pointsize ||
 		outinfo->writes_layer ||
 		outinfo->writes_viewport_index;
+	unsigned spi_vs_out_config, nparams;
 
-	radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
-	                       S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
+	/* VS is required to export at least one param. */
+	nparams = MAX2(outinfo->param_exports, 1);
+	spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
+
+	if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
+		spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
+	}
+
+	radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
 
 	radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
 	                       S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
@@ -3389,9 +3397,13 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
 		outinfo->writes_layer ||
 		outinfo->writes_viewport_index;
 	bool break_wave_at_eoi = false;
+	unsigned nparams;
 
+	nparams = MAX2(outinfo->param_exports, 1);
 	radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
-	                       S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
+	                       S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
+			       S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
+
 	radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
 			       S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
 	radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,