Mesa (master): intel/compiler: Lower gl_SubgroupSize in postprocess_nir

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Module: Mesa
Branch: master
Commit: 1981460af2c17d55c17be2475a28bbf711a80c79
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1981460af2c17d55c17be2475a28bbf711a80c79

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Feb 21 15:29:12 2019 -0600

intel/compiler: Lower gl_SubgroupSize in postprocess_nir

Instead of lowering the subgroup size so early, wait until we have more
information.  In particular, we're going to want different subgroup
sizes from different stages depending on the API.  We also defer
lowering of subgroup masks because the ge/gt masks require the subgroup
size to generate a subgroup mask.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

---

 src/intel/compiler/brw_nir.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 62e5eb7c726..6bac6636c47 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -704,10 +704,8 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
    OPT(nir_lower_system_values);
 
    const nir_lower_subgroups_options subgroups_options = {
-      .subgroup_size = BRW_SUBGROUP_SIZE,
       .ballot_bit_size = 32,
       .lower_to_scalar = true,
-      .lower_subgroup_masks = true,
       .lower_vote_trivial = !is_scalar,
       .lower_shuffle = true,
    };
@@ -811,6 +809,13 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
 
    UNUSED bool progress; /* Written by OPT */
 
+   const nir_lower_subgroups_options subgroups_options = {
+      .subgroup_size = BRW_SUBGROUP_SIZE,
+      .ballot_bit_size = 32,
+      .lower_subgroup_masks = true,
+   };
+   OPT(nir_lower_subgroups, &subgroups_options);
+
    OPT(brw_nir_lower_mem_access_bit_sizes);
 
    do {