Mesa (master): freedreno/a6xx: fix MSAA resolve hangs

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Module: Mesa
Branch: master
Commit: 010d255656d21dbac80c3bfbddcd4dbc92faa988
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=010d255656d21dbac80c3bfbddcd4dbc92faa988

Author: Rob Clark <robdclark at chromium.org>
Date:   Wed Jul 24 13:31:13 2019 -0700

freedreno/a6xx: fix MSAA resolve hangs

Seems like RB_BLIT_SCISSOR needs to be aligned to (minimum?) tile size.

Fixes intermittent GPU hangs triggered by some of the three.js samples
on https://threejs.org/

Signed-off-by: Rob Clark <robdclark at chromium.org>

---

 src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 27c57a0074c..f93dd570982 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -679,17 +679,10 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
 	struct pipe_scissor_state blit_scissor;
 	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 
-	blit_scissor.minx = batch->max_scissor.minx;
-	blit_scissor.miny = batch->max_scissor.miny;
-	blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
-	blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
-
-	/* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for
-	 * small render targets.  But since we align pitch to binw I think
-	 * we can get away avoiding GPU hangs a simpler way, by just rounding
-	 * up the blit scissor:
-	 */
-	blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw);
+	blit_scissor.minx = 0;
+	blit_scissor.miny = 0;
+	blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
+	blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
 
 	OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 	OUT_RING(ring,