Mesa (master): freedreno/ir3: Fix up the half reg source even when src instr==NULL

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Module: Mesa
Branch: master
Commit: fb53b326c24dc9f5c64f402dc53298c8b4928388
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb53b326c24dc9f5c64f402dc53298c8b4928388

Author: Neil Roberts <nroberts at igalia.com>
Date:   Fri Mar 15 14:32:27 2019 +0100

freedreno/ir3: Fix up the half reg source even when src instr==NULL

Previously the loop for assigning registers was bailing out early if
the register had a null source. I think the intention is that in this
case it isn’t necessary to assign a register. However it was also
missing out the part to fix up the types. This can happen if the
instruction is copy propagated to be a move from a constant half-float
input register. In that case it still needs to fix up the types.

Fixes assert in
dEQP-GLES3.functional.shaders.invariance.highp.subexpression_precision_mediump

when lowering the precision of the variables.

Signed-off-by: Rob Clark <robdclark at chromium.org>

---

 src/freedreno/ir3/ir3_ra.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
index 46d3e7e9044..9e7d3c7db63 100644
--- a/src/freedreno/ir3/ir3_ra.c
+++ b/src/freedreno/ir3/ir3_ra.c
@@ -1082,9 +1082,8 @@ ra_block_alloc(struct ir3_ra_ctx *ctx, struct ir3_block *block)
 		foreach_src_n(reg, n, instr) {
 			struct ir3_instruction *src = reg->instr;
 			/* Note: reg->instr could be null for IR3_REG_ARRAY */
-			if (!(src || (reg->flags & IR3_REG_ARRAY)))
-				continue;
-			reg_assign(ctx, instr->regs[n+1], src);
+			if (src || (reg->flags & IR3_REG_ARRAY))
+				reg_assign(ctx, instr->regs[n+1], src);
 			if (instr->regs[n+1]->flags & IR3_REG_HALF)
 				fixup_half_instr_src(instr);
 		}