Mesa (staging/19.1): freedreno/ir3: fix constlen versus indirect UBO

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Module: Mesa
Branch: staging/19.1
Commit: 1487faa76e8b878d2fc342494a76b061876b5fee
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1487faa76e8b878d2fc342494a76b061876b5fee

Author: Rob Clark <robdclark at chromium.org>
Date:   Fri May 31 07:40:16 2019 -0700

freedreno/ir3: fix constlen versus indirect UBO

If we access the address of the UBO indirectly, and there is no higher
const emitted w/ direct access (like an immediate lowered to uniform)
the assembler won't figure out the correct constlen.

Fixes:
  dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_vertex
  dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_fragment
  dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.dynamically_uniform_vertex
  dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.dynamically_uniform_fragment

Signed-off-by: Rob Clark <robdclark at chromium.org>
(cherry picked from commit 8b7bf5e07aafe8c3ff17fbd49e6f516b2ddab458)

---

 src/freedreno/ir3/ir3_compiler_nir.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index b8494d8aece..070f1d25971 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -697,6 +697,13 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
 	} else {
 		base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
 		base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
+
+		/* NOTE: since relative addressing is used, make sure constlen is
+		 * at least big enough to cover all the UBO addresses, since the
+		 * assembler won't know what the max address reg is.
+		 */
+		ctx->so->constlen = MAX2(ctx->so->constlen,
+			const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
 	}
 
 	/* note: on 32bit gpu's base_hi is ignored and DCE'd */
@@ -1251,7 +1258,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 			 * since we don't know in the assembler what the max
 			 * addr reg value can be:
 			 */
-			ctx->so->constlen = ctx->s->num_uniforms;
+			ctx->so->constlen = MAX2(ctx->so->constlen, ctx->s->num_uniforms);
 		}
 		break;
 	case nir_intrinsic_load_ubo: