Mesa (staging/19.0): freedreno/ir3: set more barrier bits

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Module: Mesa
Branch: staging/19.0
Commit: 214409b09e5f1f28d60e0151d82ce5d912dbcc84
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=214409b09e5f1f28d60e0151d82ce5d912dbcc84

Author: Rob Clark <robdclark at chromium.org>
Date:   Thu May 30 09:04:57 2019 -0700

freedreno/ir3: set more barrier bits

Blob is also setting the .l bit, and it seems to solve some intermittent
failures with a couple of deqp's:

dEQP-GLES31.functional.image_load_store.2d.qualifiers.coherent_r32i
dEQP-GLES31.functional.image_load_store.2d.qualifiers.volatile_r32f

Signed-off-by: Rob Clark <robdclark at chromium.org>
Acked-by: Eric Anholt <eric at anholt.net>
(cherry picked from commit f9fa456e1d09f1a6b2dccde056b3754f3f198ba7)

---

 src/freedreno/ir3/ir3_compiler_nir.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 01b4ac02b6d..fc882c2d2d1 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1511,6 +1511,7 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 		barrier->cat7.g = true;
 		barrier->cat7.r = true;
 		barrier->cat7.w = true;
+		barrier->cat7.l = true;
 		barrier->barrier_class = IR3_BARRIER_IMAGE_W |
 				IR3_BARRIER_BUFFER_W;
 		barrier->barrier_conflict =