Mesa (staging/19.0): freedreno/a6xx: fix GPU crash on small render targets
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Tue Jun 4 16:15:28 UTC 2019
Module: Mesa
Branch: staging/19.0
Commit: 6bf0ccb6f5e85bdfc01ff84f7836b9561605f9a3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bf0ccb6f5e85bdfc01ff84f7836b9561605f9a3
Author: Rob Clark <robdclark at chromium.org>
Date: Fri May 31 07:07:57 2019 -0700
freedreno/a6xx: fix GPU crash on small render targets
Fixes dEQP-GLES2.functional.multisampled_render_to_texture.readpixels
Signed-off-by: Rob Clark <robdclark at chromium.org>
Acked-by: Eric Anholt <eric at anholt.net>
(cherry picked from commit 8eaa2d502131bdce874603f522eabc4a5719f2e6)
---
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index cb5c582476f..38825d0aa4d 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -588,6 +588,13 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
+ /* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for
+ * small render targets. But since we align pitch to binw I think
+ * we can get away avoiding GPU hangs a simpler way, by just rounding
+ * up the blit scissor:
+ */
+ blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw);
+
OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
OUT_RING(ring,
A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
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