Mesa (master): panfrost/midgard: Set int outmod for "pasted" code

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Module: Mesa
Branch: master
Commit: c54f3f42eb3b8544de76e98f74d5e149b808a4f7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c54f3f42eb3b8544de76e98f74d5e149b808a4f7

Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date:   Wed May 22 02:40:41 2019 +0000

panfrost/midgard: Set int outmod for "pasted" code

These snippets of integer assembly are injected for various purposes.
Eventually, we'll want to implement these in NIR directly. Regardless,
the "default" output modifier is different between floats and ints, so
let's set the right one.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Reviewed-by: Ryan Houdek <Sonicadvance1 at gmail.com>

---

 src/gallium/drivers/panfrost/midgard/midgard_compile.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 8433c4d32b2..afa272e1e5c 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -586,6 +586,7 @@ emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned co
                 },
                 .alu = {
                         .op = midgard_alu_op_iand,
+                        .outmod = midgard_outmod_int,
                         .reg_mode = midgard_reg_mode_32,
                         .dest_override = midgard_dest_override_none,
                         .mask = (0x3 << 6), /* w */
@@ -624,6 +625,7 @@ emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
                 },
                 .alu = {
                         .op = midgard_alu_op_iand,
+                        .outmod = midgard_outmod_int,
                         .reg_mode = midgard_reg_mode_32,
                         .dest_override = midgard_dest_override_none,
                         .mask = expand_writemask((1 << nr_comp) - 1),
@@ -654,6 +656,7 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src)
                 },
                 .alu = {
                         .op = midgard_alu_op_imov,
+                        .outmod = midgard_outmod_int,
                         .reg_mode = midgard_reg_mode_32,
                         .dest_override = midgard_dest_override_none,
                         .mask = (0x3 << 6), /* w */
@@ -2775,6 +2778,7 @@ emit_blend_epilogue(compiler_context *ctx)
                         .op = midgard_alu_op_imov,
                         .reg_mode = midgard_reg_mode_8,
                         .dest_override = midgard_dest_override_none,
+                        .outmod = midgard_outmod_int,
                         .mask = 0xFF,
                         .src1 = vector_alu_srco_unsigned(blank_alu_src),
                         .src2 = vector_alu_srco_unsigned(blank_alu_src),