Mesa (19.1): 21 new commits

Wed Jun 5 16:34:59 UTC 2019

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d8f104f395012e89f55b7620c8567052b790f32
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date:   Wed Jun 5 16:23:45 2019 +0000

    Update version to 19.1.0-rc5

    Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a45ddd42d8a3f0788f789c0341c113772660008
Author: Vinson Lee <vlee at freedesktop.org>
Date:   Thu May 30 14:47:37 2019 -0700

    freedreno: Fix GCC build error.

    ../src/freedreno/vulkan/tu_device.c:900:4: error: initializer element is not constant
        .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
        ^

    Suggested-by: Kristian Høgsberg <krh at bitplanet.net>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110698
    Signed-off-by: Vinson Lee <vlee at freedesktop.org>
    Reviewed-by: Rob Clark <robdclark at gmail.com>
    (cherry picked from commit d4e70be7396b5330fca5b5ece2327a3e1c42b6e7)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=96fbd54398b7cff91bd61d6dd874fd3b2fd54c1c
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed May 22 18:23:27 2019 -0400

    ac: fix a typo in ac_build_wg_scan_bottom

    Cc: 19.1 <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
    (cherry picked from commit c9b64b58dee89ac78d38358f7ebd75cf0d6b86dd)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=60688cc393080c1dc02cf8b2cf3ef785f40902b9
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Wed May 29 16:07:44 2019 +0100

    ac/nir: mark some texture intrinsics as convergent

    Otherwise LLVM can sink them and their texture coordinate calculations
    into divergent branches.

    v2: simplify the conditions on which the intrinsic is marked as convergent
    v3: only mark as convergent in FS and CS with derivative groups

    Cc: <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    (cherry picked from commit 73dda85512942e67991a5fbc3c9a1714e7624d00)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=38927a35a6c1ad4dc26bcfb606b4e9c0f262ba4e
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Jun 3 17:52:56 2019 +0200

    radv: do not use gfx fast depth clears for layered depth/stencil images

    The driver should only fast depth clears with the graphics path
    when the view covers all image layers, otherwise this might
    corrupt layers when HTILE is enabled.

    Cc: 19.0 19.1 mesa-stable at lists.freedesktop.org
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
    Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    (cherry picked from commit 8a35eb0602735194f2976000ddff9dca2c8b5741)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf6472e780855a99f2f054002f12480c0f9cc5dd
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date:   Mon Apr 15 23:26:47 2019 -0700

    intel/compiler: Fix assertions in brw_alu3

    v2: Fix assertion for src1 (Ian Romanick)

    Fixes: 3b967e17 (intel/compiler: Avoid false positive assertions)
    Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Suggested-by: Matt Turner <mattst88 at gmail.com>
    Reviewed-by: Matt Turner <mattst88 at gmail.com>
    (cherry picked from commit 3016756398c988e965ed189cfd99dc94ddb16626)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5394f1578c1047774caf6ab9dd3f51b45a54a85c
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date:   Fri May 31 14:39:46 2019 +0200

    radeonsi: init sctx->dma_copy before using it

    Commit a1378639ab19 reordered context functions initializations but broke
    sctx->b.resource_copy_region init when using AMD_DEBUG=forcedma.

    In this case sctx->dma_copy was assigned a value after being used in:
       sctx->b.resource_copy_region = sctx->dma_copy;

    This commit moves the FORCE_DMA special case after sctx->dma_copy initialization.

    See https://bugs.freedesktop.org/show_bug.cgi?id=110422

    Signed-off-by: Marek Olšák <marek.olsak at amd.com>
    (cherry picked from commit 4583f09caa5aef719a1eec282f24a86c789cbba6)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=51998d720b3d6fba0dce99f54bc3532e37694b04
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date:   Wed May 29 13:13:44 2019 +1000

    st/glsl: make sure to propagate initialisers to driver storage

    This essentially reverts 20234cfe3a20.

    Fixes piglit test:
    tests/spec/arb_get_program_binary/execution/uniform-after-restore.shader_test

    Fixes: 20234cfe3a20 "st/mesa: don't propagate uniforms when restoring from cache"

    Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110784
    (cherry picked from commit fea36a8f43ea010ce0581a63b4b5fa1213a35982)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8773e2023899e054def4409db4a15aa0a6a4c3c6
Author: Axel Davy <davyaxel0 at gmail.com>
Date:   Sun May 26 22:59:30 2019 +0200

    d3dadapter9: Revert to old throttling limit value

    Recently PIPE_CAP_MAX_FRAMES_IN_FLIGHT was changed from 2
    to 1:
    20909284f204091757c050aa40cfffaf3f981b9c

    No driver seems to overwrite the default value.

    One user reports severe regressions for some games.
    For now, revert to the value 2 for nine.

    Cc: "19.1" mesa-stable at lists.freedesktop.org

    Signed-off-by: Axel Davy <davyaxel0 at gmail.com>
    (cherry picked from commit 5820ac6756898a1bd30bde04555437a55c378726)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4524f09cc098bb8b3ca22b2c9960a8c3e92e04af
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon May 27 18:47:31 2019 -0400

    u_blitter: don't fail mipmap generation for depth formats containing stencil

    Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=109754

    Cc: 19.0 19.1 <mesa-stable at lists.freedesktop.org>
    Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    (cherry picked from commit 4b11ed443b85e4fcddc5d0ef60dec096ecdb951e)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fce389c8b7dad2179ff939d7be8dfe38454bee9
Author: Rob Clark <robdclark at chromium.org>
Date:   Fri May 31 07:07:57 2019 -0700

    freedreno/a6xx: fix GPU crash on small render targets

    Fixes dEQP-GLES2.functional.multisampled_render_to_texture.readpixels

    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Acked-by: Eric Anholt <eric at anholt.net>
    (cherry picked from commit 8eaa2d502131bdce874603f522eabc4a5719f2e6)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a37f10af7be93f87573b44de979dafd6821d5e59
Author: Rob Clark <robdclark at chromium.org>
Date:   Thu May 30 09:04:57 2019 -0700

    freedreno/ir3: set more barrier bits

    Blob is also setting the .l bit, and it seems to solve some intermittent
    failures with a couple of deqp's:

    dEQP-GLES31.functional.image_load_store.2d.qualifiers.coherent_r32i
    dEQP-GLES31.functional.image_load_store.2d.qualifiers.volatile_r32f

    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Acked-by: Eric Anholt <eric at anholt.net>
    (cherry picked from commit f9fa456e1d09f1a6b2dccde056b3754f3f198ba7)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=90d045f993ffea449560b8d73788e0a8aec20602
Author: Jonathan Marek <jonathan at marek.ca>
Date:   Fri May 31 12:17:06 2019 -0400

    freedreno/ir3: fix input ncomp for vertex shaders

    ncomp is never set for vertex shaders, but a3xx and a4xx still use it.

    Fixes: 831f1a05c0d freedreno/ir3: rework varying packing

    Signed-off-by: Jonathan Marek <jonathan at marek.ca>
    Reviewed-by: Rob Clark <robdclark at chromium.org>
    (cherry picked from commit 1db86d8b62860380c34af77ae62b019ed2376443)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2c5c1666870d23df395e97642e67be57fe4f4de
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Thu May 30 22:48:46 2019 +0200

    nir: Actually propagate progress in nir_opt_move_load_ubo.

    Found with Jasons new metadata rework (https://gitlab.freedesktop.org/mesa/mesa/merge_requests/950).

    Fixes: af355aaa071 "nir: add nir_opt_move_load_ubo() optimization pass"
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
    Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
    (cherry picked from commit e24a7840f60ac2290761ea2dc2831e8c3ba8bbfc)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fecdcce09cb9ddf70fb4d7b89b8a117a0620d575
Author: Jan Zielinski <jan.zielinski at intel.com>
Date:   Mon May 27 14:15:53 2019 +0200

    swr/rast: fix 32-bit compilation on Linux

    Removing unused but problematic code from simdlib header to fix
    compilation problem on 32-bit Linux.

    Reviewed-by: Alok Hota <alok.hota at intel.com>
    (cherry picked from commit cf673747cefca03c2b672db6788c1ac2af6d9f33)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a13bda4957662b8c2ccd6b749492549b8c09f30d
Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Wed May 22 22:13:15 2019 -0500

    nir/dead_cf: Call instructions aren't dead

    When we inlined cf_node_has_side_effects into node_is_dead, all the
    conditions flipped and we forgot to flip one.  Fortunately, it doesn't
    matter right now because no one uses this pass on shaders with more than
    one function.

    Fixes: b50465d197 "nir/dead_cf: Inline cf_node_has_side_effects"
    Reviewed-by: Dave Airlie <airlied at redhat.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    (cherry picked from commit 8948048c6f01209bac0051e41cd84c38853bd251)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2a945771cfa2d3a17f2fbacdab6e497872ddd76
Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Wed May 22 12:36:17 2019 -0500

    intel/fs: Do a stalling MFENCE in endInvocationInterlock()

    Fixes: 939312702e "i965: Add ARB_fragment_shader_interlock support"
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    (cherry picked from commit 9e403dc56e3ab702abc68fd65ed4ab324ba69e69)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=92f4a16af8f5dd467e374ff6d9ef4fbeca7b1e8f
Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Wed May 22 12:20:01 2019 -0500

    intel/fs,vec4: Use g0 as the header for MFENCE

    We set header_present but then pass it some random garbage.  Give it g0
    instead.  I'm not actually sure this does anything but g0 is the usual
    header data and this is what the windows driver does so it seems like a
    good idea.

    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    (cherry picked from commit 859de4a74857d2736f6e2dd9d2fd98b92bbc69d9)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a19270007c272b12d271807767421b8965411def
Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Tue May 28 21:56:04 2019 -0500

    iris: Don't assume UBO indices are constant

    It will be true for the constant/system value buffer because they use a
    constant zero but it's not true in general.  If we ever got here when
    the source wasn't constant, nir_src_as_uint would assert.

    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Cc: mesa-stable at lists.freedesktop.org
    (cherry picked from commit 9dc57eebd578b976b94c54d083377ba0920d43a8)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c7dfaba9c49e2a37e0019833e356908422084c8
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Tue May 28 08:52:50 2019 +0100

    nir/lower_non_uniform: safely iterate over blocks

    This fixes a problem where the same instruction gets replaced twice.
    This was happening when the replaced instruction would be at the end
    of a block.

    Replacement of :

       if ssa_8 {
                    ....
          intrinsic bindless_image_store (ssa_44, ssa_16, ssa_0, ssa_15) (5, 0, 34836, 32) /* image_dim=Buf */ /* image_array=false */ /* format=34836 */ /* access=32 */
       }

    Would be :

       if ssa_8 {
          loop {
             vec1 32 ssa_47 = intrinsic read_first_invocation (ssa_44) ()
             vec1 1 ssa_48 = ieq ssa_47, ssa_44
             if ssa_48 {
                loop {
                   vec1 32 ssa_49 = intrinsic read_first_invocation (ssa_44) ()
                   vec1 1 ssa_50 = ieq ssa_49, ssa_44
                   if ssa_50 {
                      intrinsic bindless_image_store (ssa_44, ssa_16, ssa_0, ssa_15) (5, 0, 34836, 32) /* image_dim=Buf */ /* image_array=false */ /* format=34836 */ /* access=32 */
                      break
                   } else {
            ....
       }

    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
    Fixes: 3bd545764151 ("nir: Add a lowering pass for non-uniform resource access")
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    (cherry picked from commit 366811bedb67ae7d31a02ea9b1f9fa942fb93602)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=411114c45ceabf5a2b62c1c7968ad306bb8d2058
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue May 28 12:58:05 2019 +0200

    radv: allocate more space in the CS when emitting events

    If the driver waits for CP DMA to be idle and emit an EOP event
    we need more space.

    This fixes a crash with Quake Champions.

    Cc: <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
    Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    (cherry picked from commit 47a10edefb3510d1cae071037dac78a46b31949b)