Mesa (master): panfrost/midgard: Add a bunch of new ALU ops
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Wed Jun 5 18:00:22 UTC 2019
Module: Mesa
Branch: master
Commit: 9f14e20fa1fdb36ff8a014d9f4e2c4a2fba7b588
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f14e20fa1fdb36ff8a014d9f4e2c4a2fba7b588
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date: Wed Jun 5 15:18:35 2019 +0000
panfrost/midgard: Add a bunch of new ALU ops
These ops are used to accelerate various functions exposed in OpenCL.
This commit only includes the routine additions to the table. They are
not wired through the compiler; rather, they are just here to keep a
reference for the disassembler.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Reviewed-By: Ryan Houdek <Sonicadvance1 at gmail.com>
---
src/gallium/drivers/panfrost/midgard/midgard.h | 14 +++++++++++++-
src/gallium/drivers/panfrost/midgard/midgard_compile.c | 5 ++++-
src/gallium/drivers/panfrost/midgard/midgard_ops.c | 17 +++++++++++++++--
3 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard.h b/src/gallium/drivers/panfrost/midgard/midgard.h
index f5cd59cbfb1..7bf17321ccb 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard.h
+++ b/src/gallium/drivers/panfrost/midgard/midgard.h
@@ -75,6 +75,10 @@ typedef enum {
midgard_alu_op_iadd = 0x40,
midgard_alu_op_ishladd = 0x41,
midgard_alu_op_isub = 0x46,
+ midgard_alu_op_iaddsat = 0x48,
+ midgard_alu_op_uaddsat = 0x49,
+ midgard_alu_op_isubsat = 0x4E,
+ midgard_alu_op_usubsat = 0x4F,
midgard_alu_op_imul = 0x58,
@@ -82,6 +86,10 @@ typedef enum {
midgard_alu_op_umin = 0x61,
midgard_alu_op_imax = 0x62,
midgard_alu_op_umax = 0x63,
+ midgard_alu_op_ihadd = 0x64,
+ midgard_alu_op_uhadd = 0x65,
+ midgard_alu_op_irhadd = 0x66,
+ midgard_alu_op_urhadd = 0x67,
midgard_alu_op_iasr = 0x68,
midgard_alu_op_ilsr = 0x69,
midgard_alu_op_ishl = 0x6E,
@@ -97,7 +105,9 @@ typedef enum {
midgard_alu_op_iclz = 0x78, /* Number of zeroes on left */
midgard_alu_op_ibitcount8 = 0x7A, /* Counts bits in 8-bit increments */
midgard_alu_op_imov = 0x7B,
- midgard_alu_op_iabs = 0x7C,
+ midgard_alu_op_iabsdiff = 0x7C,
+ midgard_alu_op_uabsdiff = 0x7D,
+ midgard_alu_op_ichoose = 0x7E, /* vector, component number - dupe for shuffle() */
midgard_alu_op_feq = 0x80,
midgard_alu_op_fne = 0x81,
@@ -146,6 +156,8 @@ typedef enum {
midgard_alu_op_fatan_pt2 = 0xE8,
midgard_alu_op_fpow_pt1 = 0xEC,
+ midgard_alu_op_fpown_pt1 = 0xED,
+ midgard_alu_op_fpowr_pt1 = 0xEE,
midgard_alu_op_frcp = 0xF0,
midgard_alu_op_frsqrt = 0xF2,
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 0f3331d923b..96f3e525b4a 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -682,7 +682,10 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
ALU_CASE(iadd, iadd);
ALU_CASE(isub, isub);
ALU_CASE(imul, imul);
- ALU_CASE(iabs, iabs);
+
+ /* Zero shoved as second-arg */
+ ALU_CASE(iabs, iabsdiff);
+
ALU_CASE(mov, imov);
ALU_CASE(feq32, feq);
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ops.c b/src/gallium/drivers/panfrost/midgard/midgard_ops.c
index cffa3c20fdf..97c12feec00 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_ops.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_ops.c
@@ -40,6 +40,11 @@ struct mir_op_props alu_opcode_props[256] = {
[midgard_alu_op_imax] = {"imax", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_umin] = {"umin", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_umax] = {"umax", UNITS_MOST | OP_COMMUTES},
+ [midgard_alu_op_ihadd] = {"ihadd", UNITS_ADD | OP_COMMUTES},
+ [midgard_alu_op_uhadd] = {"uhadd", UNITS_ADD | OP_COMMUTES},
+ [midgard_alu_op_irhadd] = {"irhadd", UNITS_ADD | OP_COMMUTES},
+ [midgard_alu_op_urhadd] = {"urhadd", UNITS_ADD | OP_COMMUTES},
+
[midgard_alu_op_fmov] = {"fmov", UNITS_ALL | QUIRK_FLIPPED_R24},
[midgard_alu_op_fround] = {"fround", UNITS_ADD},
[midgard_alu_op_froundeven] = {"froundeven", UNITS_ADD},
@@ -56,8 +61,14 @@ struct mir_op_props alu_opcode_props[256] = {
/* Incredibly, iadd can run on vmul, etc */
[midgard_alu_op_iadd] = {"iadd", UNITS_MOST | OP_COMMUTES},
- [midgard_alu_op_iabs] = {"iabs", UNITS_ADD},
+ [midgard_alu_op_iaddsat] = {"iaddsat", UNITS_ADD | OP_COMMUTES},
+ [midgard_alu_op_uaddsat] = {"uaddsat", UNITS_ADD | OP_COMMUTES},
+ [midgard_alu_op_iabsdiff] = {"iabsdiff", UNITS_ADD},
+ [midgard_alu_op_uabsdiff] = {"uabsdiff", UNITS_ADD},
+ [midgard_alu_op_ichoose] = {"ichoose", UNITS_ADD},
[midgard_alu_op_isub] = {"isub", UNITS_MOST},
+ [midgard_alu_op_isubsat] = {"isubsat", UNITS_MOST},
+ [midgard_alu_op_usubsat] = {"usubsat", UNITS_MOST},
[midgard_alu_op_imul] = {"imul", UNITS_MUL | OP_COMMUTES},
[midgard_alu_op_imov] = {"imov", UNITS_MOST | QUIRK_FLIPPED_R24},
@@ -74,7 +85,7 @@ struct mir_op_props alu_opcode_props[256] = {
[midgard_alu_op_ule] = {"ule", UNITS_MOST},
[midgard_alu_op_icsel] = {"icsel", UNITS_ADD},
- [midgard_alu_op_icsel_v] = {"icsel_v", UNITS_ADD},
+ [midgard_alu_op_icsel_v] = {"icsel_v", UNITS_ADD}, /* Acts as bitselect() */
[midgard_alu_op_fcsel_v] = {"fcsel_v", UNITS_ADD},
[midgard_alu_op_fcsel] = {"fcsel", UNITS_ADD | UNIT_SMUL},
@@ -82,6 +93,8 @@ struct mir_op_props alu_opcode_props[256] = {
[midgard_alu_op_frsqrt] = {"frsqrt", UNIT_VLUT},
[midgard_alu_op_fsqrt] = {"fsqrt", UNIT_VLUT},
[midgard_alu_op_fpow_pt1] = {"fpow_pt1", UNIT_VLUT},
+ [midgard_alu_op_fpown_pt1] = {"fpown_pt1", UNIT_VLUT},
+ [midgard_alu_op_fpowr_pt1] = {"fpowr_pt1", UNIT_VLUT},
[midgard_alu_op_fexp2] = {"fexp2", UNIT_VLUT},
[midgard_alu_op_flog2] = {"flog2", UNIT_VLUT},
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