Mesa (master): freedreno: Stop treating UBO 0 specially in UBO uploading.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 852704976aa9b8ddbdc4fee83b95612f88189668
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=852704976aa9b8ddbdc4fee83b95612f88189668

Author: Eric Anholt <eric at anholt.net>
Date:   Wed Jun  5 10:34:52 2019 -0700

freedreno: Stop treating UBO 0 specially in UBO uploading.

ir3_nir_analyze_ubo_ranges() has already told us how much of cb0 we
need to upload (all of it, since it will lower indirect UBO 0 accesses
from load_ubo back to indirection on the constant buffer).

Reviewed-by: Kristian H. Kristensen <hoegsberg at google.com>
Reviewed-by: Rob Clark <robdclark at gmail.com>

---

 src/freedreno/ir3/ir3_nir.c                     |  2 --
 src/freedreno/ir3/ir3_shader.h                  |  5 ----
 src/gallium/drivers/freedreno/ir3/ir3_gallium.c | 34 +------------------------
 3 files changed, 1 insertion(+), 40 deletions(-)

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 320e485b98d..437f196bbe0 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -351,8 +351,6 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
 
 	ir3_nir_scan_driver_consts(nir, const_state);
 
-	const_state->num_uniforms = nir->num_uniforms;
-
 	debug_assert((shader->ubo_state.size % 16) == 0);
 	unsigned constoff = align(shader->ubo_state.size / 16, 4);
 	unsigned ptrsz = ir3_pointer_size(compiler);
diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index 61654b75f8f..b3291896f4d 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -110,11 +110,6 @@ enum ir3_driver_param {
  * Note UBO size in bytes should be aligned to vec4
  */
 struct ir3_const_state {
-	/* number of uniforms (in vec4), not including built-in compiler
-	 * constants, etc.
-	 */
-	unsigned num_uniforms;
-
 	unsigned num_ubos;
 
 	struct {
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
index 3315afb9144..fde02aa23c9 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
@@ -204,42 +204,10 @@ static void
 emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
 		struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 {
-	const unsigned index = 0;     /* user consts are index 0 */
-
-	if (constbuf->enabled_mask & (1 << index)) {
-		struct pipe_constant_buffer *cb = &constbuf->cb[index];
-		/* size in dwords, aligned to vec4.  (This works at least
-		 * with mesa/st, which seems to align constant buffer to
-		 * 16 bytes)
-		 */
-		unsigned size = align(cb->buffer_size, 16) / 4;
-
-		/* in particular, with binning shader we may end up with
-		 * unused consts, ie. we could end up w/ constlen that is
-		 * smaller than first_driver_param.  In that case truncate
-		 * the user consts early to avoid HLSQ lockup caused by
-		 * writing too many consts
-		 */
-		const struct ir3_const_state *const_state = &v->shader->const_state;
-		uint32_t max_const = MIN2(const_state->num_uniforms, v->constlen);
-
-		/* and even if the start of the const buffer is before
-		 * first_immediate, the end may not be:
-		 */
-		size = MIN2(size, 4 * max_const);
-
-		if (size > 0) {
-			ring_wfi(ctx->batch, ring);
-			ctx->emit_const(ring, v->type, 0,
-					cb->buffer_offset, size,
-					cb->user_buffer, cb->buffer);
-		}
-	}
-
 	struct ir3_ubo_analysis_state *state;
 	state = &v->shader->ubo_state;
 
-	for (uint32_t i = 1; i < ARRAY_SIZE(state->range); i++) {
+	for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
 		struct pipe_constant_buffer *cb = &constbuf->cb[i];
 
 		if (state->range[i].start < state->range[i].end &&