Mesa (master): radeonsi: flatten the switch for DPBB tunables
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Tue Jun 25 01:05:15 UTC 2019
Module: Mesa
Branch: master
Commit: f46efacd01c8f503b239dd16122ec6de5a684877
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f46efacd01c8f503b239dd16122ec6de5a684877
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 19 22:24:51 2019 -0400
radeonsi: flatten the switch for DPBB tunables
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
---
src/gallium/drivers/radeonsi/si_state_binning.c | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 6285ccc28c2..a6b1830b661 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -402,20 +402,10 @@ void si_emit_dpbb_state(struct si_context *sctx)
unsigned persistent_states_per_bin; /* allowed range: [0, 31] */
unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
- switch (sctx->family) {
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_RAVEN2:
- /* Tuned for Raven. Vega might need different values. */
- context_states_per_bin = 5;
- persistent_states_per_bin = 31;
- fpovs_per_batch = 63;
- break;
- default:
- assert(0);
- }
+ /* Tuned for Raven. Vega might need different values. */
+ context_states_per_bin = 5;
+ persistent_states_per_bin = 31;
+ fpovs_per_batch = 63;
/* Emit registers. */
struct uvec2 bin_size_extend = {};
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