Mesa (master): virgl: Don't allow creating staging pipe_resources
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Fri Jun 28 04:38:42 UTC 2019
Module: Mesa
Branch: master
Commit: 7da90a7cc909f691f97473be1e864aeccd5a587b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7da90a7cc909f691f97473be1e864aeccd5a587b
Author: Alexandros Frantzis <alexandros.frantzis at collabora.com>
Date: Thu Jun 27 10:48:50 2019 +0300
virgl: Don't allow creating staging pipe_resources
Staging buffers are now created directly by the virgl_staging_mgr. We
don't need to support creating staging pipe_resources.
Signed-off-by: Alexandros Frantzis <alexandros.frantzis at collabora.com>
Reviewed-by: Chia-I Wu <olvaffe at gmail.com>
---
src/gallium/drivers/virgl/virgl_buffer.c | 6 ------
src/gallium/drivers/virgl/virgl_resource.h | 20 ++++++++------------
src/gallium/drivers/virgl/virgl_texture.c | 6 ------
3 files changed, 8 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/virgl/virgl_buffer.c b/src/gallium/drivers/virgl/virgl_buffer.c
index bc12f3f8876..fb97ce15aae 100644
--- a/src/gallium/drivers/virgl/virgl_buffer.c
+++ b/src/gallium/drivers/virgl/virgl_buffer.c
@@ -90,12 +90,6 @@ static void virgl_buffer_transfer_unmap(struct pipe_context *ctx,
{
struct virgl_context *vctx = virgl_context(ctx);
struct virgl_transfer *trans = virgl_transfer(transfer);
- struct virgl_screen *vs = virgl_screen(ctx->screen);
- struct pipe_resource *res = transfer->resource;
-
- /* We don't transfer the contents of staging resources, since they don't
- * have any host-side storage. */
- assert(pipe_to_virgl_bind(vs, res->bind, res->flags) != VIRGL_BIND_STAGING);
if (trans->base.usage & PIPE_TRANSFER_WRITE) {
if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
diff --git a/src/gallium/drivers/virgl/virgl_resource.h b/src/gallium/drivers/virgl/virgl_resource.h
index 47aefb4bd38..f41c1ce98b3 100644
--- a/src/gallium/drivers/virgl/virgl_resource.h
+++ b/src/gallium/drivers/virgl/virgl_resource.h
@@ -33,12 +33,6 @@
#include "virgl_screen.h"
#define VR_MAX_TEXTURE_2D_LEVELS 15
-/* Indicates that the resource will be used as a staging buffer, not requiring
- * dedicated host-side storage. Can only be used with PIPE_BUFFER resources
- * that have a PIPE_BIND_CUSTOM bind type.
- */
-#define VIRGL_RESOURCE_FLAG_STAGING (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
-
struct winsys_handle;
struct virgl_screen;
struct virgl_context;
@@ -144,12 +138,8 @@ static inline unsigned pipe_to_virgl_bind(const struct virgl_screen *vs,
outbind |= VIRGL_BIND_STREAM_OUTPUT;
if (pbind & PIPE_BIND_CURSOR)
outbind |= VIRGL_BIND_CURSOR;
- if (pbind & PIPE_BIND_CUSTOM) {
- if (flags & VIRGL_RESOURCE_FLAG_STAGING)
- outbind |= VIRGL_BIND_STAGING;
- else
- outbind |= VIRGL_BIND_CUSTOM;
- }
+ if (pbind & PIPE_BIND_CUSTOM)
+ outbind |= VIRGL_BIND_CUSTOM;
if (pbind & PIPE_BIND_SCANOUT)
outbind |= VIRGL_BIND_SCANOUT;
if (pbind & PIPE_BIND_SHARED)
@@ -161,6 +151,12 @@ static inline unsigned pipe_to_virgl_bind(const struct virgl_screen *vs,
if (pbind & PIPE_BIND_COMMAND_ARGS_BUFFER)
if (vs->caps.caps.v2.capability_bits & VIRGL_CAP_BIND_COMMAND_ARGS)
outbind |= VIRGL_BIND_COMMAND_ARGS;
+
+ /* Staging resources should only be created directly through the winsys,
+ * not using pipe_resources.
+ */
+ assert(!(outbind & VIRGL_BIND_STAGING));
+
return outbind;
}
diff --git a/src/gallium/drivers/virgl/virgl_texture.c b/src/gallium/drivers/virgl/virgl_texture.c
index 8a85a28cec4..f33b3f8808d 100644
--- a/src/gallium/drivers/virgl/virgl_texture.c
+++ b/src/gallium/drivers/virgl/virgl_texture.c
@@ -313,14 +313,8 @@ static void virgl_texture_transfer_unmap(struct pipe_context *ctx,
{
struct virgl_context *vctx = virgl_context(ctx);
struct virgl_transfer *trans = virgl_transfer(transfer);
- struct virgl_screen *vs = virgl_screen(ctx->screen);
- struct pipe_resource *res = transfer->resource;
bool queue_unmap = false;
- /* We don't transfer the contents of staging resources, since they don't
- * have any host-side storage. */
- assert(pipe_to_virgl_bind(vs, res->bind, res->flags) != VIRGL_BIND_STAGING);
-
if (transfer->usage & PIPE_TRANSFER_WRITE &&
(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) == 0) {
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