Mesa (master): Revert "i965/icl: Add WA_2204188704 to disable pixel shader panic dispatch"

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Module: Mesa
Branch: master
Commit: 7746d4edef5332777bd0206e836617879ad8bb70
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7746d4edef5332777bd0206e836617879ad8bb70

Author: Anuj Phogat <anuj.phogat at gmail.com>
Date:   Wed Jun 26 14:19:53 2019 -0700

Revert "i965/icl: Add WA_2204188704 to disable pixel shader panic dispatch"

SLICE_COMMON_CHICKEN3 is a privileged register not accesible from userspace.
This patch silences a simulator warning about it.

We don't need to add this workaround in linux kernel as the WA description
says it's fixed on latest stepping.

This reverts commit 85ecd14ef6a084f5e82860de6dbc79870b335682.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

---

 src/mesa/drivers/dri/i965/brw_defines.h      | 4 ----
 src/mesa/drivers/dri/i965/brw_state_upload.c | 6 ------
 2 files changed, 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 17bca1991f1..f0096e996b5 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1676,10 +1676,6 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GLK_SCEC_BARRIER_MODE_MASK        REG_MASK(1 << 7)
 # define GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE (1 << 11)
 
-#define COMMON_SLICE_CHICKEN3              0x7304
-# define PS_THREAD_PANIC_DISPATCH          (3 << 6)
-# define PS_THREAD_PANIC_DISPATCH_MASK     REG_MASK(3 << 6)
-
 #define HALF_SLICE_CHICKEN7                0xE194
 # define TEXEL_OFFSET_FIX_ENABLE           (1 << 1)
 # define TEXEL_OFFSET_FIX_MASK             REG_MASK(1 << 1)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 938b9defeda..c41d9551a1e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -109,12 +109,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
       brw_load_register_imm32(brw, GEN8_L3CNTLREG,
                               GEN8_L3CNTLREG_EDBC_NO_HANG);
 
-      /* WA_2204188704: Pixel Shader Panic dispatch must be disabled.
-       */
-       brw_load_register_imm32(brw, COMMON_SLICE_CHICKEN3,
-                               PS_THREAD_PANIC_DISPATCH_MASK |
-                               PS_THREAD_PANIC_DISPATCH);
-
        /* WaEnableStateCacheRedirectToCS:icl */
        brw_load_register_imm32(brw, SLICE_COMMON_ECO_CHICKEN1,
                                GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE |