Mesa (master): intel/fs: Relax type matching rules in cmod propagation from MOV instructions

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Module: Mesa
Branch: master
Commit: c9d5bd050c31b6ca20610a5eadd27068bd5c190b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9d5bd050c31b6ca20610a5eadd27068bd5c190b

Author: Ian Romanick <ian.d.romanick at intel.com>
Date:   Tue Jun 19 13:34:57 2018 -0700

intel/fs: Relax type matching rules in cmod propagation from MOV instructions

To allow cmod propagation from a MOV in a sequence like:

    and(16)         g31<1>UD       g20<8,8,1>UD   g22<8,8,1>UD
    mov.nz.f0(16)   null<1>F       g31<8,8,1>D

A similar change to the vec4 backend had no effect.

Somewhere between c1ec5820593 and 40fc4b5acd6 (1,094 commits) the
effectiveness of this patch diminished, and as of commit d7e0d47b9de
(nir: Add a bunch of b2[if] optimizations) this optimization no longer
has any effect on any platform.

A later patch "intel/fs: Use De Morgan's laws to avoid logical-not of a
logic result on Gen8+," generates some instruction sequences that
require this change in order for cmod propagation to make progress.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/intel/compiler/brw_fs_cmod_propagation.cpp | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs_cmod_propagation.cpp b/src/intel/compiler/brw_fs_cmod_propagation.cpp
index b58730fbbe5..14852e52e6e 100644
--- a/src/intel/compiler/brw_fs_cmod_propagation.cpp
+++ b/src/intel/compiler/brw_fs_cmod_propagation.cpp
@@ -263,10 +263,25 @@ opt_cmod_propagation_local(const gen_device_info *devinfo, bblock_t *block)
                break;
 
             /* Comparisons operate differently for ints and floats */
-            if (scan_inst->dst.type != inst->dst.type &&
-                (scan_inst->dst.type == BRW_REGISTER_TYPE_F ||
-                 inst->dst.type == BRW_REGISTER_TYPE_F))
-               break;
+            if (scan_inst->dst.type != inst->dst.type) {
+               /* We should propagate from a MOV to another instruction in a
+                * sequence like:
+                *
+                *    and(16)         g31<1>UD       g20<8,8,1>UD   g22<8,8,1>UD
+                *    mov.nz.f0(16)   null<1>F       g31<8,8,1>D
+                */
+               if (inst->opcode == BRW_OPCODE_MOV) {
+                  if ((inst->src[0].type != BRW_REGISTER_TYPE_D &&
+                       inst->src[0].type != BRW_REGISTER_TYPE_UD) ||
+                      (scan_inst->dst.type != BRW_REGISTER_TYPE_D &&
+                       scan_inst->dst.type != BRW_REGISTER_TYPE_UD)) {
+                     break;
+                  }
+               } else if (scan_inst->dst.type == BRW_REGISTER_TYPE_F ||
+                          inst->dst.type == BRW_REGISTER_TYPE_F) {
+                  break;
+               }
+            }
 
             /* If the instruction generating inst's source also wrote the
              * flag, and inst is doing a simple .nz comparison, then inst