Mesa (master): v3d: Stop treating exec masking specially.

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Module: Mesa
Branch: master
Commit: fd1d22b92edbf98e2ec10c880b2703bfdb0f3b62
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd1d22b92edbf98e2ec10c880b2703bfdb0f3b62

Author: Eric Anholt <eric at anholt.net>
Date:   Mon Mar  4 22:11:15 2019 -0800

v3d: Stop treating exec masking specially.

In our backend, the successor edges from the blocks only point to where
QPU control flow goes, not where the notional control flow goes from a
"break" or "continue" modifying the execution mask to resume writing to
some channels later.  As a result, this attempt at restricting live ranges
ended up missing the live range of a value where a conditional
break/continue was present in a loop before the later def of a variable.
The previous commit ended up fixing the problem that the flag tried to
solve.

Fixes glsl-vs-loop-continue.shader_test and/or
glsl-vs-loop-redundant-condition.shader_test based on register allocation
results.

---

 src/broadcom/compiler/nir_to_vir.c         |  1 -
 src/broadcom/compiler/v3d_compiler.h       |  1 -
 src/broadcom/compiler/vir_live_variables.c | 15 +++------------
 3 files changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c
index 5d2c872f2aa..d4f6088bcf2 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -405,7 +405,6 @@ ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
                         c->cursor = vir_after_inst(last_inst);
 
                         vir_set_cond(last_inst, V3D_QPU_COND_IFA);
-                        last_inst->cond_is_exec_mask = true;
                 }
         }
 }
diff --git a/src/broadcom/compiler/v3d_compiler.h b/src/broadcom/compiler/v3d_compiler.h
index 75dff07404e..11d4cc3b7b1 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -134,7 +134,6 @@ struct qinst {
         /* Pre-register-allocation references to src/dst registers */
         struct qreg dst;
         struct qreg src[3];
-        bool cond_is_exec_mask;
         bool has_implicit_uniform;
         bool is_last_thrsw;
 
diff --git a/src/broadcom/compiler/vir_live_variables.c b/src/broadcom/compiler/vir_live_variables.c
index cba4000fd1d..d3ca02f1882 100644
--- a/src/broadcom/compiler/vir_live_variables.c
+++ b/src/broadcom/compiler/vir_live_variables.c
@@ -118,18 +118,9 @@ vir_setup_def(struct v3d_compile *c, struct qblock *block, int ip,
         if (BITSET_TEST(block->use, var) || BITSET_TEST(block->def, var))
                 return;
 
-        /* Easy, common case: unconditional full register update.
-         *
-         * We treat conditioning on the exec mask as the same as not being
-         * conditional.  This makes sure that if the register gets set on
-         * either side of an if, it is treated as being screened off before
-         * the if.  Otherwise, if there was no intervening def, its live
-         * interval doesn't extend back to the start of he program, and if too
-         * many registers did that we'd fail to register allocate.
-         */
-        if (((inst->qpu.flags.ac == V3D_QPU_COND_NONE &&
-              inst->qpu.flags.mc == V3D_QPU_COND_NONE) ||
-             inst->cond_is_exec_mask) &&
+        /* Easy, common case: unconditional full register update.*/
+        if ((inst->qpu.flags.ac == V3D_QPU_COND_NONE &&
+             inst->qpu.flags.mc == V3D_QPU_COND_NONE) &&
             inst->qpu.alu.add.output_pack == V3D_QPU_PACK_NONE &&
             inst->qpu.alu.mul.output_pack == V3D_QPU_PACK_NONE) {
                 BITSET_SET(block->def, var);