Mesa (master): isl: Add a swizzle parameter to isl_buffer_fill_state()

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Module: Mesa
Branch: master
Commit: 4787bc944a2d219dd04201eef699d9f999b479b8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4787bc944a2d219dd04201eef699d9f999b479b8

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Feb 28 01:13:33 2019 -0800

isl: Add a swizzle parameter to isl_buffer_fill_state()

This is necessary for legacy texture buffer object formats, where we'll
need to use a swizzle to fake e.g. luminance.

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

---

 src/gallium/drivers/iris/iris_state.c            | 3 +++
 src/intel/isl/isl.h                              | 5 +++++
 src/intel/isl/isl_surface_state.c                | 8 ++++----
 src/intel/vulkan/anv_device.c                    | 1 +
 src/intel/vulkan/anv_image.c                     | 1 +
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 1 +
 6 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index ec39225716c..592b2c48ade 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1560,6 +1560,7 @@ fill_buffer_surface_state(struct isl_device *isl_dev,
                          .address = bo->gtt_offset + offset,
                          .size_B = final_size,
                          .format = format,
+                         .swizzle = ISL_SWIZZLE_IDENTITY,
                          .stride_B = cpp,
                          .mocs = mocs(bo));
 }
@@ -2352,6 +2353,7 @@ upload_ubo_surf_state(struct iris_context *ice,
                          .size_B = MIN2(buffer_size,
                                         res->bo->size - cbuf->data.offset),
                          .format = ISL_FORMAT_R32G32B32A32_FLOAT,
+                         .swizzle = ISL_SWIZZLE_IDENTITY,
                          .stride_B = 1,
                          .mocs = mocs(res->bo))
 }
@@ -2509,6 +2511,7 @@ iris_set_shader_buffers(struct pipe_context *ctx,
                                   MIN2(buffer->buffer_size,
                                        res->bo->size - buffer->buffer_offset),
                                .format = ISL_FORMAT_RAW,
+                               .swizzle = ISL_SWIZZLE_IDENTITY,
                                .stride_B = 1,
                                .mocs = mocs(res->bo));
       } else {
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index cfac922a3d2..a792e18e5d1 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1361,6 +1361,11 @@ struct isl_buffer_fill_state_info {
     */
    enum isl_format format;
 
+   /**
+    * The swizzle to use in the surface state
+    */
+   struct isl_swizzle swizzle;
+
    uint32_t stride_B;
 };
 
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 7ab260d701b..cf31b36ccbe 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -745,10 +745,10 @@ isl_genX(buffer_fill_state_s)(void *state,
 #endif
 
 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
-   s.ShaderChannelSelectRed = SCS_RED;
-   s.ShaderChannelSelectGreen = SCS_GREEN;
-   s.ShaderChannelSelectBlue = SCS_BLUE;
-   s.ShaderChannelSelectAlpha = SCS_ALPHA;
+   s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
+   s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
+   s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
+   s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
 #endif
 
    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 92e8f40278f..963f108a0e8 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -3324,6 +3324,7 @@ anv_fill_buffer_surface_state(struct anv_device *device, struct anv_state state,
                          .mocs = device->default_mocs,
                          .size_B = range,
                          .format = format,
+                         .swizzle = ISL_SWIZZLE_IDENTITY,
                          .stride_B = stride);
 }
 
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index facf7d18006..dfa72cbfe6c 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -1203,6 +1203,7 @@ anv_image_fill_surface_state(struct anv_device *device,
                             .address = anv_address_physical(address),
                             .size_B = surface->isl.size_B,
                             .format = ISL_FORMAT_RAW,
+                            .swizzle = ISL_SWIZZLE_IDENTITY,
                             .stride_B = 1,
                             .mocs = anv_mocs_for_bo(device, address.bo));
       state_inout->address = address,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a0984791614..8175fbf0db4 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -647,6 +647,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
                                                     reloc_flags),
                          .size_B = buffer_size,
                          .format = surface_format,
+                         .swizzle = ISL_SWIZZLE_IDENTITY,
                          .stride_B = pitch,
                          .mocs = brw_get_bo_mocs(devinfo, bo));
 }