Mesa (master): radv: store more vertex attribute infos as pipeline keys
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Wed Mar 13 12:31:19 UTC 2019
Module: Mesa
Branch: master
Commit: 0b9a06a1a0e4f4b7130a5c372d13b586a8d66878
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b9a06a1a0e4f4b7130a5c372d13b586a8d66878
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Feb 26 13:42:27 2019 +0100
radv: store more vertex attribute infos as pipeline keys
They are required for using typed buffer loads.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
---
src/amd/vulkan/radv_pipeline.c | 27 +++++++++++++++++++++++++++
src/amd/vulkan/radv_private.h | 4 ++++
src/amd/vulkan/radv_shader.h | 6 ++++++
3 files changed, 37 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 55dbe0620a6..60510f97e0f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1903,6 +1903,9 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
key.vertex_attribute_formats[location] = data_format | (num_format << 4);
+ key.vertex_attribute_bindings[location] = desc->binding;
+ key.vertex_attribute_offsets[location] = desc->offset;
+ key.vertex_attribute_strides[location] = input_state->pVertexBindingDescriptions[desc->binding].stride;
if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
@@ -1927,6 +1930,26 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
}
key.vertex_alpha_adjust |= adjust << (2 * location);
}
+
+ switch (desc->format) {
+ case VK_FORMAT_B8G8R8A8_UNORM:
+ case VK_FORMAT_B8G8R8A8_SNORM:
+ case VK_FORMAT_B8G8R8A8_USCALED:
+ case VK_FORMAT_B8G8R8A8_SSCALED:
+ case VK_FORMAT_B8G8R8A8_UINT:
+ case VK_FORMAT_B8G8R8A8_SINT:
+ case VK_FORMAT_B8G8R8A8_SRGB:
+ case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
+ case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
+ case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
+ case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
+ case VK_FORMAT_A2R10G10B10_UINT_PACK32:
+ case VK_FORMAT_A2R10G10B10_SINT_PACK32:
+ key.vertex_post_shuffle |= 1 << location;
+ break;
+ default:
+ break;
+ }
}
if (pCreateInfo->pTessellationState)
@@ -1955,9 +1978,13 @@ radv_fill_shader_keys(struct radv_shader_variant_key *keys,
{
keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
+ keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
+ keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
+ keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
+ keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
}
if (nir[MESA_SHADER_TESS_CTRL]) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 27b5a9e77cd..c73bdaca0a3 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -366,7 +366,11 @@ struct radv_pipeline_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
uint64_t vertex_alpha_adjust;
+ uint32_t vertex_post_shuffle;
unsigned tess_input_vertices;
uint32_t col_format;
uint32_t is_int8;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index d9fc64aeb9a..fe2f2868630 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -66,11 +66,17 @@ struct radv_vs_variant_key {
uint32_t instance_rate_inputs;
uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
+ uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
/* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
* so we may need to fix it up. */
uint64_t alpha_adjust;
+ /* For some formats the channels have to be shuffled. */
+ uint32_t post_shuffle;
+
uint32_t as_es:1;
uint32_t as_ls:1;
uint32_t export_prim_id:1;
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