Mesa (staging/19.0): i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9
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gitlab-mirror at kemper.freedesktop.org
Thu Mar 14 17:05:15 UTC 2019
Module: Mesa
Branch: staging/19.0
Commit: 35029d4361809cf5c04eea442b617eaf08cd89fd
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=35029d4361809cf5c04eea442b617eaf08cd89fd
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Tue Mar 12 21:25:36 2019 +0200
i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9
ARB_fragment_shader_interlock depends on memory fences to
ensure fragment ordering and this ordering guarantee is
only supported from GEN9 onwards.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109980
Fixes: 939312702e35 "i965: Add ARB_fragment_shader_interlock support."
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 19ab08200179e71af42ce6e1b91f502e50f915b3)
---
src/intel/compiler/brw_fs_generator.cpp | 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 25 ++++++++++++++++++++++++-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index fb77ece30ca..09382775f3e 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2100,6 +2100,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
break;
case SHADER_OPCODE_INTERLOCK:
+ assert(devinfo->gen >= 9);
/* The interlock is basically a memory fence issued via sendc */
brw_memory_fence(p, dst, BRW_OPCODE_SENDC);
break;
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index a9730ba66fe..92ecd612006 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -253,7 +253,6 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.EXT_shader_samples_identical = true;
ctx->Extensions.OES_primitive_bounding_box = true;
ctx->Extensions.OES_texture_buffer = true;
- ctx->Extensions.ARB_fragment_shader_interlock = true;
if (can_do_pipelined_register_writes(brw->screen)) {
ctx->Extensions.ARB_draw_indirect = true;
@@ -318,6 +317,30 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.KHR_blend_equation_advanced_coherent = true;
ctx->Extensions.KHR_texture_compression_astc_ldr = true;
ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
+
+ /*
+ * From the Skylake PRM Vol. 7 (Memory Fence Message, page 221):
+ * "A memory fence message issued by a thread causes further messages
+ * issued by the thread to be blocked until all previous data port
+ * messages have completed, or the results can be globally observed from
+ * the point of view of other threads in the system."
+ *
+ * From the Haswell PRM Vol. 7 (Memory Fence, page 256):
+ * "A memory fence message issued by a thread causes further messages
+ * issued by the thread to be blocked until all previous messages issued
+ * by the thread to that data port (data cache or render cache) have
+ * been globally observed from the point of view of other threads in the
+ * system."
+ *
+ * Summarized: For ARB_fragment_shader_interlock to work, we need to
+ * ensure memory access ordering for all messages to the dataport from
+ * all threads. Memory fence messages prior to SKL only provide memory
+ * access ordering for messages from the same thread, so we can only
+ * support the feature from Gen9 onwards.
+ *
+ */
+
+ ctx->Extensions.ARB_fragment_shader_interlock = true;
}
if (gen_device_info_is_9lp(devinfo))
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