Mesa (fast-color-clear): 574 new commits
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Thu Mar 14 20:38:25 UTC 2019
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea0c633d2754e554705e464e59f446ba224ee404
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Thu Mar 14 22:35:19 2019 +0200
i965: Re-enable fast color clear for GEN11.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=183c63cb995cf4e7ee29474fafd8c973a402c1f7
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Thu Mar 14 22:34:29 2019 +0200
i965: Clarify when to skip color clear.
In certain cases we can't skip a color clear
even if the aux_state is ISL_AUX_STATE_CLEAR,
for instance if the clear color has changed or
the aux_usage is ISL_AUX_USAGE_MCS.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4480ea118885789973f23dee6a3a47808a6c85e3
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Thu Mar 14 22:31:10 2019 +0200
i965: Set clear color with MI_ATOMIC for GEN11.
For GEN11 we need to set the clear color using two
MI_ATOMIC commands.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b71316904ed1b141c77be4fe915884543529067
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Thu Mar 14 22:28:20 2019 +0200
isl: Set ClearColorConversionEnable.
The ClearColorConversionEnable bit needs to be set
for GEN11 when inderect clear colors are used.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36cd05170264801bc1d41ed372044d228ea0333d
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Thu Mar 14 22:23:41 2019 +0200
i965: Add BRW_AOP_MOV8 to brw_eu_defines.h
BRW_AOP_MOV8 performs an atomic MOV on 8 bytes
of data.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5142d4c161d8891edfc3252dd541230aed44c3d4
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Thu Mar 14 22:20:43 2019 +0200
i965: Add opcode for MI_ATOMIC to brw_defines.h
MI_ATOMIC is used to carry out atomic operations
on data in graphics memory.
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16d108b502370b31cad7438a3e53b25554840f47
Author: Mark Janes <mark.a.janes at intel.com>
Date: Thu Dec 6 16:35:44 2018 -0800
mesa: add logging function for formatted string
Reviewed-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8a1a3214afa3ac8f3b46ecce59bdd75a612c7e9
Author: Mark Janes <mark.a.janes at intel.com>
Date: Thu Dec 6 16:35:43 2018 -0800
mesa: rename logging functions to reflect that they format strings
In preparation for the definition of a function to log a formatted
string.
Reviewed-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb1a869a5d19bfd8a0d4099afd58f180997e4663
Author: Mark Janes <mark.a.janes at intel.com>
Date: Thu Dec 6 16:35:42 2018 -0800
mesa: properly report the length of truncated log messages
_mesa_log_msg must provide the length of the string passed into the
KHR_debug api. When the string formatted by _mesa_gl_vdebugf exceeds
MAX_DEBUG_MESSAGE_LENGTH, the length is incorrectly set to the number
of characters that would have been written if enough space had been
available.
Fixes: 30256805784450b8bb9d4dabfb56226271ca9d24
("mesa: Add support for GL_ARB_debug_output with dynamic ID allocation.")
Reviewed-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=162286eb7529d469f64b83e11ff896ac3549add6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Mar 13 17:27:39 2019 -0500
anv: Only set 3DSTATE_PS::VectorMaskEnable on gen8+
We don't set it on HSW and earlier in i965 and disabling it appears to
make derivatives somewhat more reliable.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b63fe65bf680dac516e935f3b1608a7bc046a132
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Thu Mar 14 12:30:15 2019 +0000
travis: fix osx meson build
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a2e93147f7fa4a6fd17313353113a33291c5ce0
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Mar 14 14:27:03 2019 +0100
radv: always initialize HTILE when the src layout is UNDEFINED
HTILE should always be initialized when transitioning from
VK_IMAGE_LAYOUT_UNDEFINED to other image layouts. Otherwise,
if an app does a transition from UNDEFINED to GENERAL, the
driver doesn't initialize HTILE and it tries to decompress
the depth surface. For some reasons, this results in VM faults.
Cc: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107563
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=27b0661e30a8217dd94623b13232fd62a943b1eb
Author: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Date: Thu Mar 14 15:20:50 2019 +0100
panfrost: Adapt to uapi changes
Two ioctls had wrong DRM_IO* flags.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Reviewed-by: Rob Herring <robh at kernel.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=19ab08200179e71af42ce6e1b91f502e50f915b3
Author: Plamena Manolova <plamena.manolova at intel.com>
Date: Tue Mar 12 21:25:36 2019 +0200
i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9
ARB_fragment_shader_interlock depends on memory fences to
ensure fragment ordering and this ordering guarantee is
only supported from GEN9 onwards.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109980
Fixes: 939312702e35 "i965: Add ARB_fragment_shader_interlock support."
Signed-off-by: Plamena Manolova <plamena.n.manolova at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c3adaad22c34742058a9f52138cfd37778ef6df
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 13 15:35:28 2019 -0700
iris: Don't mutate box in transfer map code
Not mutating the boxes is arguably cleaner.
Split from a patch by Chris Wilson but reworked to use a pointer to the
original box rather than making a copy at all.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b41175c22e14775656e13d11ca84cad83837b04
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Mar 13 12:13:09 2019 +0200
i965: remove scaling factors from P010, P012
Patch removes scaling factors introduced in 2a2e69f975b but leaves
option to use scaling in place as it could be useful with other upcoming
YUV formats.
We did this scaling because ffmpeg was shifting channel bits down, however
it seems this is not the right place as compositor wants to flip same
buffers directly to display as well and therefore bitshifting needs to be
done by the client when receiving frame from ffmpeg.
Now P0x formats are treated the same, e.g. P010 is same as P016 but with
lower 6 bits set to zeros.
Fixes: 2a2e69f975b "i965: add P0x formats and propagate required scaling factors"
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=489bf2de237a190b966a412efda89d12d1daacde
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 12 22:55:14 2019 -0500
anv/pass: Flag the need for a RT flush for resolve attachments
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Cc: mesa-stable at lists.freedesktop.org
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13099d4490a7445f370b3f895c2eb082cd7e2f0a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 12 15:22:19 2019 -0500
anv: Stop using VK_TRUE/FALSE
We've been fairly inconsistent about this so we should really choose
whether we're going to use VK_TRUE/FALSE or the C boolean values. The
Vulkan #defines are set to 1 and 0 respectively so it's the same value
as C gives you when you cast a boolean expression to an integer. Since
there are several places where we set a VkBool32 to a C logical
expression, let's just embrace C booleans and stop using the VK defines.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6dc68e7b5b6f76a55037f6995dad101cc089d02
Author: Gurchetan Singh <gurchetansingh at chromium.org>
Date: Wed Mar 13 22:58:22 2019 +0000
virgl: use uint16_t mask instead of separate booleans
This should save some space.
Suggested-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=56717e13a65007a641ede756ea0b26a333dbc72b
Author: Albert Pal <liviuprodea at yahoo.com>
Date: Wed Mar 13 20:28:06 2019 +0000
Fix link release notes for 19.0.0.
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b2b449dd146c43860c71eb05f0f02ee2ad69854
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Thu Feb 21 17:51:26 2019 -0800
iris: Enable auxiliary buffer support again
Now that we are properly resolving buffers before giving them to the
window system, let's enable aux support again.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1281368d02a22d08a892fbfda4cecc1219cde895
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Thu Mar 7 15:32:38 2019 -0800
iris: Convert RGBX to RGBA always.
In i965, we disable the use of RGBX formats, so the higher layers of
Mesa choose the equivalent RGBA format, and swizzle the alpha channel to
1.0.
However, Gallium won't do that. We need to explicitly convert it to
RGBA.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9159a5bbf882f94c48c21371049fef2d03d3dafd
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Thu Feb 28 11:08:32 2019 -0800
iris: Add resolve on iris_flush_resource.
The flush_resource hook is supposedly called when the resource content
needs to be made visible to external (okay, that's pretty vague). For
instance, it gets called before a surface gets handled to the window
system. So we need to resolve it if it's not resolved yet.
v2 (Ken):
- Check mod_info in iris_flush_resource instead of ISL_AUX_USAGE_NONE
- Drop my old broken resolve code from iris_resource_get_handle() now
that Rafael's got it hooked up in the right place.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=759ceda07e122e3b2cc7a5e44698f41accb5e92c
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Feb 28 18:17:50 2019 +0100
ir3/lower_io_offsets: Try propagate SSBO's SHR into a previous shift instruction
While we lack value range tracking, this patch tries to 'manually' propogate
the division by 4 to calculate SSBO element-offset, into a possible previous
shift operation (shift left or right); checking that it is safe to do so.
This should help in cases like ie. when accessing a field in an array of
structs, where the offset is likely defined as base plus a multiplication
by a struct or array element size.
See dEQP test 'dEQP-GLES31.functional.ssbo.atomic.xor.highp_uint'
for an example of a shader that benefits from this.
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e4525883f0744b0c8df9792ded597090a8ad987
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Feb 26 14:07:04 2019 +0100
ir3/compiler: Enable lower_io_offsets pass and handle new SSBO intrinsics
These intrinsics have the offset in dwords already computed in the last
source, so the change here is basically using that instead of emitting
the ir3_SHR to divide the byte-offset by 4.
The improvement in shader stats is significant, of up to ~15% in
instruction count in some cases. Tested only on a5xx.
shader-db is unfortunately not very useful here because shaders that use
SSBO require GLSL versions that are not supported by freedreno yet.
For examples, most Khronos CTS tests under 'dEQP-GLES31.functional.ssbo.*'
are helped.
A random case:
dEQP-GLES31.functional.ssbo.layout.2_level_array.packed.row_major_mat3x2
with current master:
; CL prog 14/1: 1252 instructions, 0 half, 48 full
; 8 const, 8 constlen
; 61 (ss), 43 (sy)
with the SSBO dword-offset moved to NIR:
; CL prog 14/1: 1053 instructions, 0 half, 45 full
; 7 const, 7 constlen
; 34 (ss), 73 (sy)
The SHR previously emitted for every single SSBO instruction disappears
in most cases, and the dword-offset ends up embedded in the STGB
instruction as immediate in many cases as well.
There are also a few of those tests that are currently failing on register
allocation, that start to pass as a result of reducing the pressure. At least
these, probably more:
dEQP-GLES31.functional.ssbo.layout.random.unsized_arrays.24
dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6
dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.17
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays.14
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.5
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.7
No regressions observed with relevant CTS and piglit tests.
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9dd0cfafc9ec4b4efb1e2df0329afc7a5a534231
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Sun Jan 13 20:10:34 2019 +0100
ir3/nir: Add a new pass 'ir3_nir_lower_io_offsets'
This NIR->NIR pass implements offset computations that are currently
done on the IR3 backend compiler, to give NIR a better chance of
optimizing them.
For now, it supports lowering the dword-offset computation for SSBO
instructions. It will take an SSBO intrinsic and replace it with the
new ir3-specific version that adds an extra source. That source will
hold the SSA value resulting from inserting a division by 4 (an SHR op)
of the original byte-offset source already provided by NIR in one of
the intrinsic sources.
Note that on a6xx the original byte-offset is not needed, so we could
potentially replace that source instead of adding a new one. But to
keep things simple and consistent we always add the new source and
a6xx will just ignore the original one.
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ff50a488a12f86069bff88e3ad1b6473a76f014
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Feb 26 08:45:07 2019 +0100
nir: Add ir3-specific version of most SSBO intrinsics
These are ir3 specific versions of SSBO intrinsics that add an
extra source to hold the element offset (dword), which is what the
backend instructions need.
The original byte-offset source provided by NIR is not replaced
because on a4xx and a5xx the backend still needs it.
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03a0801bcb1828d785d8f7ef46a4000a8e0c1ce1
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Mar 13 12:36:27 2019 -0700
docs: update calendar, add news item, and link release notes for 19.0.0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cd487f3754494f61630a1922004a0852d87eb07
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Mar 13 12:09:08 2019 -0700
docs: Add SHA256 sums for 19.0.0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=44273b4806fcf7c26bdcea43ae55cc634fe1d324
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Mar 13 10:40:19 2019 -0700
docs: Add release notes for 19.0.0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=70b36c0ef939048acb9c4727b2e4280fc090eb74
Author: Kevin Strasser <kevin.strasser at intel.com>
Date: Mon Jan 28 10:42:44 2019 -0800
egl/dri: Avoid out of bounds array access
indexConfigAttrib iterates over every index in the dri driver, possibly
exceeding __DRI_ATTRIB_MAX. In other words, if the dri driver has newer
attributes libEGL will end up reading from uninitialized memory through
dri2_to_egl_attribute_map[].
Signed-off-by: Kevin Strasser <kevin.strasser at intel.com>
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=97ad0efba08d336813366b9cab114c94c2ca61db
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Feb 22 20:53:41 2019 +0000
iris: Use streaming loads to read from tiled surfaces
Always use the streaming load (since we know we have Broadwell+, all of
our target CPU support sse41) for reading back form the tiled surface
for mapping the resource. This means we hit the fast WC handling paths
on Atoms (without LLC), and for big Core (with LLC) using the streaming
load is no less efficient as we do not require the tiled buffer to be
pulled into the CPU cache.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=797fb6c6ac96cb7d1d5f9a04dc4f22f350093a16
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Feb 22 21:24:46 2019 +0000
iris: Use coherent allocation for PIPE_RESOURCE_STAGING
On !llc machines (Atoms), reading from a linear buffers is slow and so
copying from one resource into the linear staging buffer is still slow.
However, we can tell the GPU to snoop the CPU cache when reading from and
writing to the staging buffer eliminating the slow uncached reads.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01b224047b0013380a5e8b709eaf2e3cd9976b39
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Feb 25 09:42:49 2019 +0000
iris: Use PIPE_BUFFER_STAGING for the query objects
We prefer fast CPU access to read back the query results.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=65e8761474ca8c9c0cce167cb32b720c3cc25a90
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Mon Mar 11 09:43:04 2019 -0700
intel/nir: Combine store_derefs to improve code from SPIR-V
Due to lack of write mask in SPIR-V store, generators may produce
multiple stores to the same vector but using different array derefs.
Use the combining store pass to clean this up. For example,
layout(binding = 3) buffer block {
vec4 v;
};
void main() {
v.x = 11;
v.y = 22;
}
after going to SPIR-V and NIR, ends up with in two store_derefs to
v[0] and v[1]
vec2 32 ssa_4 = deref_struct &ssa_3->field0 (ssbo vec4) /* &((block *)ssa_2)->field0 */
vec2 32 ssa_6 = deref_array &(*ssa_4)[0] (ssbo float) /* &((block *)ssa_2)->field0[0] */
intrinsic store_deref (ssa_6, ssa_7) (1, 0) /* wrmask=x */ /* access=0 */
vec1 32 ssa_13 = load_const (0x00000001 /* 0.000000 */)
vec2 32 ssa_14 = deref_array &(*ssa_4)[1] (ssbo float) /* &((block *)ssa_2)->field0[1] */
intrinsic store_deref (ssa_14, ssa_15) (1, 0) /* wrmask=x */ /* access=0 */
producing two different sends instructions in skl. The combining pass
transform the snippet above into
vec2 32 ssa_4 = deref_struct &ssa_3->field0 (ssbo vec4) /* &((block *)ssa_2)->field0 */
vec4 32 ssa_18 = vec4 ssa_7, ssa_15, ssa_16, ssa_17
intrinsic store_deref (ssa_4, ssa_18) (3, 0) /* wrmask=xy */ /* access=0 */
producing a single sends instruction.
v2: Move this from spirv_to_nir into the general optimization pass for
intel compiler. (Jason)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=10dfb0011e7079e770184d252045c13c40e6b274
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Fri Mar 8 11:50:47 2019 -0800
intel/nir: Combine store_derefs after vectorizing IO
Shader-db results for skl:
total instructions in shared programs: 15232903 -> 15224781 (-0.05%)
instructions in affected programs: 61246 -> 53124 (-13.26%)
helped: 221
HURT: 0
total cycles in shared programs: 371440470 -> 371398018 (-0.01%)
cycles in affected programs: 281363 -> 238911 (-15.09%)
helped: 221
HURT: 0
Results for bdw are very similar.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=822a8865e4645ed7e1818568d1d0338b462c7748
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Fri Mar 8 10:08:20 2019 -0800
nir: Add a pass to combine store_derefs to same vector
v2: (all from Jason)
Reuse existing function for the end of the block combinations.
Check the SSA values are coming from the right place in tests.
Document the case when the store to array_deref is reused.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cbf022cb316f1224f9afcc12ca414fc2d7d778a8
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Mar 13 14:04:14 2019 +0100
ac: use the raw tbuffer version for 16-bit SSBO loads
vindex is always 0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=045fae0f734a39cd24e444ac05382545dc7fdd2e
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Mar 13 14:04:13 2019 +0100
ac: add ac_build_{struct,raw}_tbuffer_load() helpers
The struct version sets IDXEN=1, while the raw version sets IDXEN=0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a66b186bebf9b63897199b9b6e26d40977417f74
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Feb 26 13:42:28 2019 +0100
radv: use typed buffer loads for vertex input fetches
This drastically reduces the number of SGPRs because the driver
now uses descriptors per vertex binding, instead of per vertex
attribute format.
29077 shaders in 15096 tests
Totals:
SGPRS: 1354285 -> 1282109 (-5.33 %)
VGPRS: 909896 -> 908800 (-0.12 %)
Spilled SGPRs: 24840 -> 24811 (-0.12 %)
Code Size: 49221144 -> 48986628 (-0.48 %) bytes
Max Waves: 243930 -> 244229 (0.12 %)
Totals from affected shaders:
SGPRS: 390648 -> 318472 (-18.48 %)
VGPRS: 288432 -> 287336 (-0.38 %)
Spilled SGPRs: 94 -> 65 (-30.85 %)
Code Size: 11548412 -> 11313896 (-2.03 %) bytes
Max Waves: 86460 -> 86759 (0.35 %)
This gives a really tiny boost.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b9a06a1a0e4f4b7130a5c372d13b586a8d66878
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Feb 26 13:42:27 2019 +0100
radv: store more vertex attribute infos as pipeline keys
They are required for using typed buffer loads.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=489dac0d21baf069cf0045e785330eb1b16094a4
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Feb 26 13:42:26 2019 +0100
ac: rework typed buffers loads for LLVM 7
Be more generic, this will be used by an upcoming series.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=56e04f67f906aea6101ba6081c5b0efcc25999cc
Author: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Date: Mon Mar 11 13:35:27 2019 +0100
panfrost: Set bo->gem_handle when creating a linear BO
So we can free it later.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfbad30543dd896459b09e0e05bc70ea1727e0b9
Author: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Date: Mon Mar 11 13:34:53 2019 +0100
panfrost: Set bo->size[0] in the DRM backend
So we can unmap it later.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3570d15b6d88bdcd353b31ffe5460d04a88b7b6f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 11 19:00:21 2019 -0700
intel/fs: Fix opt_peephole_csel to not throw away saturates.
We were not copying the saturate bit from the original instruction
to the new replacement instruction. This caused major misrendering
in DiRT Rally on iris, where comparisons leading to discards failed
due to the missing saturate, causing lots of extra garbage pixels to
be drawn in text rendering, trees, and so on.
This did not show up on i965 because st/nir performs a more aggressive
version of nir_opt_peephole_select, yielding more b32csel operations.
Fixes: 52c7df1643e i965/fs: Merge CMP and SEL into CSEL on Gen8+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd17bdc56b34a08c421172df27fe07294c7a7024
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 11 20:43:15 2019 -0500
glsl/lower_vector_derefs: Don't use a temporary for TCS outputs
Tessellation control shader outputs act as if they have memory backing
them and you can have multiple writes to different components of the
same vector in-flight at the same time. When this happens, the load vec
store pattern that gets used by ir_triop_vector_insert doesn't yield the
correct results. Instead, just emit a sequence of conditional
assignments.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: mesa-stable at lists.freedesktop.org
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=20c4578c5539de909e94a6acc3ad680ab2ddeca6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 11 21:01:34 2019 -0500
glsl/list: Add a list variant of insert_after
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=83fdefc06287f6c8bbb3bb5bb4ccd36d653017a3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 12 16:25:39 2019 -0500
nir/loop_unroll: Fix out-of-bounds access handling
The previous code was completely broken when it came to constructing the
undef values. I'm not sure how it ever worked. For the case of a copy
that reads an undefined value, we can just delete the copy because the
destination is a valid undefined value. This saves us the effort of
trying to construct a value for an arbitrary copy_deref intrinsic.
Fixes: e8a8937a04 "nir: add partial loop unrolling support"
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c056609c439da964db8344a8fde66aec4bd9c877
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 12 18:18:58 2019 -0500
anv: Ignore VkRenderPassInputAttachementAspectCreateInfo
We don't care about the information but there's no sense in throwing a
debug warning about it. It's harmless but annoying to users.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109984
Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=486b181fd758c246c2d1eaa1975a858e84d64c32
Author: Eric Anholt <eric at anholt.net>
Date: Tue Mar 12 14:59:21 2019 -0700
v3d: Fix leak of the renderonly struct on screen destruction.
This makes v3d match vc4's destroy path.
Fixes: e113b21cb779 ("v3d: Add renderonly support.")
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c874c18cd07539f56fede272a24b76f2946716f
Author: Eric Anholt <eric at anholt.net>
Date: Tue Mar 12 14:56:57 2019 -0700
v3d: Fix leak of the mem_ctx after the DAG refactor.
Noticed while trying to get a CTS run again.
Fixes: 33886474d646 ("v3d: Use the DAG datastructure for QPU instruction scheduling.")
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=acfd88204e886e671da97b895fd2d1ee39b61256
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Thu Aug 3 20:07:58 2017 +0200
glx: add support for GLX_ARB_create_context_no_error (v3)
v2: Only reject no-error contexts for too-old GL if we're actually
trying to create a no-error context (Adam Jackson)
v3: Fix share contexts (Adam Jackson)
Reviewed-by: Adam Jackson <ajax at redhat.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae77f1236862e73c1ac250898924c648d481bda4
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Mar 12 21:49:42 2019 +0100
radv: set the maximum number of IBs per submit to 192
This fixes random SteamVR corruption, see
https://github.com/ValveSoftware/SteamVR-for-Linux/issues/181
Fixes: 4d30f2c6f42 ("radv/winsys: remove the max IBs per submit limit for the fallback path")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c80be956fff4d4786a9b77c6b9d3fec67ff2377
Author: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Date: Tue Mar 12 17:13:47 2019 +0200
anv: Fix destroying descriptor sets when pool gets reset
pool->next and pool->free_list were reset before their usage in
anv_descriptor_pool_free_set
Fixes: 775aabdd "anv: destroy descriptor sets when pool gets reset"
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccce9409470c1053c40c822d759b9bd417062bc0
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 11 15:59:24 2019 -0700
v3d: Disable PIPE_CAP_BLIT_BASED_TEXTURE_TRANSFER.
This reduces the runtime of dEQP-GLES3.functional.shaders.precision.* from
11.5s to 3.3s. This brings CTS runs down to 4 hours on one of my target
devices.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d5d89d25a0a4299dbfcbfeca71b6c7e65ef3d45
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Mar 7 15:01:37 2019 -0600
intel/nir: Vectorize all IO
The IO scalarization pass that we run to help with linking end up
turning some shader I/O such as that for tessellation and geometry
shaders into many scalar URB operations rather than one vector one. To
alleviate this, we now vectorize the I/O once again. This fixes a 10%
performance regression in the GfxBench tessellation test that was caused
by scalarizing.
Shader-db results on Kaby Lake:
total instructions in shared programs: 15224023 -> 15220871 (-0.02%)
instructions in affected programs: 342009 -> 338857 (-0.92%)
helped: 1236
HURT: 443
total spills in shared programs: 23471 -> 23465 (-0.03%)
spills in affected programs: 6 -> 0
helped: 1
HURT: 0
total fills in shared programs: 31770 -> 31766 (-0.01%)
fills in affected programs: 4 -> 0
helped: 1
HURT: 0
Cycles was just a lot of churn do to moves being different places. Most
of the pure churn in instructions was +/- one or two instructions in
fragment shaders.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107510
Fixes: 4434591bf56a "intel/nir: Call nir_lower_io_to_scalar_early"
Fixes: 8d8222461f9d "intel/nir: Enable nir_opt_find_array_copies"
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ef2b8f1f2ebcdb4ffe5c98b3f4f48e584cb4b22
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Mar 6 15:21:51 2019 -0600
nir: Add a pass for lowering IO back to vector when possible
This pass tries to turn scalar and array-of-scalar IO variables into
vector IO variables whenever possible.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Cc: "19.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f025bbccc236140101bc03ce9fa9d7a5bdb843b
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Dec 6 14:58:50 2018 +0000
ac/nir: fix 16-bit ssbo stores
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f89fd17ed2b1bd0c0fe4ec946dcabed0f8c74d3
Author: pal1000 <liviuprodea at yahoo.com>
Date: Thu Mar 7 10:38:10 2019 +0200
scons: Compatibility with Scons development version string
This ensures Mesa3D build doesn't fail in this case as encountered when
bisecting Scons source code while regression testing
https://bugs.freedesktop.org/show_bug.cgi?id=109443
and when testing 3.0.5.a.2
Technical details:
Scons version string has consistently been in this format:
MajorVersion.MinorVersion.Patch[.alpha/beta.yyyymmdd]
so these formulas should strip alpha/beta flags and return Scons version:
- as string - `'.'.join(SCons.__version__.split('.')[:3])`
- as tuple of integers - `tuple(map(int, SCons.__version__.split('.')[:3]))`
- v2: Fixed Scons version retrieval formulas as string and tuple of integers.
- v3: Fixed Scons version string format description.
Cc: "19.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bef354321b8e55dd68ad1769504f55fb63da1294
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Mar 12 14:01:26 2019 +0200
anv: revert "anv: release memory allocated by glsl types during spirv_to_nir"
This reverts commit 47fc359822494935852de1e70e4d840b2fe6a25c.
Reason is that patch did not take in to account situation where we might
have both OpenGL and Vulkan using glsl_types at the same time.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bbe58c214b4ff7f614bfadb5c8691a2fe47ab51
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Mon Mar 4 18:00:30 2019 +0100
radeonsi/nir: Use nir stripping pass
This reduces compilation time for my shader-db collection from around 40
seconds to 30, vs. 19 seconds for TGSI. There are still some shaders
that TGSI caches but NIR doesn't, partly because of more aggressive
cross-stage optimizations with NIR.
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b2ec9c81e1abafd19f1efbbe499df03ae4aa37e
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Mon Mar 4 17:51:12 2019 +0100
nir: Add a stripping pass for improved cacheability
Oftentimes various nir shaders after lowering will be the same, or
almost the same. For example, this can happen when the same shader is
linked with different shaders to form different pipelines and
cross-stage optimizations don't kick in to change it. We want to avoid
running the backend twice on these shaders. We were already doing this
with radeonsi, but we were storing a few extra pieces of information
that made this much less effective compared to TGSI. The worse offender
by far was the program name, which caused most of the cache misses. This
pass strips out these pieces of information, controlled by the NIR_STRIP
debug env variable.
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6403171843824ec8e9484bb8a21a4a18bfb01193
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Mar 11 10:25:53 2019 +0100
radv: fix pointSizeRange limits
The values should match the ones that are emitted.
This fixes new CTS dEQP-VK.rasterization.primitive_size.points.*.
Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbef6c2d5ff56a6a319f5d022069b05db94c74a7
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date: Wed Feb 13 22:22:16 2019 -0800
iris: Flag fewer dirty bits in BLORP
v2: 1) Skip flagging IRIS_DIRTY_DEPTH_BUFFER if
BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set (Kenneth Graunke)
2) Add missing flags (Kenneth Graunke)
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb2898f4786f9e80e0a2dd061d620fc7ced6f1ea
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Fri Mar 1 21:35:41 2019 +1100
st/glsl_to_nir: fix incorrect arrary access
This fixes a segfault when we try to access the array using a
-1 when the array wasn't allocated in the first place.
Before 7536af670b75 we would just access a pre-allocated array
that was also load/stored to/from the shader cache. But now the
cache will no longer allocate these arrays if they are empty.
The change resulted in tests such as the following segfaulting
when run with a warm shader cache.
tests/spec/arb_arrays_of_arrays/execution/sampler/fs-struct-const-index.shader_test
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=02c2863df514cf24ec6464f6daa9f299bcf542e1
Author: Brian Paul <brianp at vmware.com>
Date: Mon Mar 11 20:12:15 2019 -0600
nir: silence a couple new compiler warnings
[33/630] Compiling C object 'src/compiler/nir/nir at sta/nir_loop_analyze.c.o'.
../src/compiler/nir/nir_loop_analyze.c: In function ‘try_find_trip_count_vars_in_iand’:
../src/compiler/nir/nir_loop_analyze.c:846:29: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses]
if (*ind == NULL || *ind && (*ind)->type != basic_induction ||
^
[85/630] Compiling C object 'src/compiler/nir/nir at sta/nir_opt_loop_unroll.c.o'.
../src/compiler/nir/nir_opt_loop_unroll.c: In function ‘complex_unroll_single_terminator’:
../src/compiler/nir/nir_opt_loop_unroll.c:494:17: warning: unused variable ‘unroll_loc’ [-Wunused-variable]
nir_cf_node *unroll_loc =
^
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=587ad37e72d2a343b82a0c62c41c869d6825e14d
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sat Mar 9 00:45:23 2019 +0000
panfrost: Identify fragment_extra flags
The fragment_extra structure contains additional fields extending the
MRT framebuffer descriptor, snuck in between the main framebuffer
descriptor and the render targets. Its fields include those related to
transaction elimination and depth/stencil buffers. This patch identifies
the flags field (previously just "unk" with some magic values) as well
as identifying some (but not all) flags set by the driver.
The process of identifying flags brought a bug to light where
transaction elimination (checksumming) could not be enabled unless AFBC
was in-use. This issue is now resolved.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e57ea53acf14ef8285e713f279b6c61d6b07a35d
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sat Mar 9 00:12:07 2019 +0000
panfrost: Document "depth-buffer writeback" bit
This bit, if set, causes the depth buffer to be copied from GPU tile
memory to the provided depth buffer in main memory. If not set, the GPU
will not access the main memory (saving considerable memory bandwidth if
depth results are not actually used).
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2df4537f911178e545e78aab9f3b37bb72438c00
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Fri Mar 8 23:41:12 2019 +0000
panfrost: Support linear depth textures
This combination has not yet been seen "in the wild" in traces, but to
support linear depth FBOs, ~bruteforce reveals this bit pattern is
necessary. It's not yet clear why the meanings of 0x1 and 0x2 are
essentially flipped (tiled vs linear for colour, linear vs some sort of
tiled for depth).
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f25a4e65c025364df0b52cbb3e9aa2e525b1a74
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Fri Mar 8 23:36:02 2019 +0000
panfrost: Allocate dedicated slab for linear BOs
Previously, linear BOs shared memory with each other to minimize kernel
round-trips / latency, as well as to work around a bug in the free_slab
function. These concerns are invalid now, but continuing to use the slab
allocator for BOs resulted in memory allocation errors. This issue was
aggravated, though not introduced (so not a real regression) in the
previous commit.
v2 (unreviewed): Fix bug in v1 preventing munmaps from working
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9dc1ebc0d5cc475b8729f2dc4f6dac8c83e52a1
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Thu Mar 7 04:42:49 2019 +0000
panfrost: Determine framebuffer format bits late
Again, these formats are only properly known at the time of fragment job
emit. Rather than hardcoding the format, at least for MFBD we begin to
construct the format bits on-demand. This cleans up the code,
futureproofs for ES3 framebuffer formats, and should fix bugs regarding
FBO colour swizzles.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.visozo at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ba18cdfa9a6e54f802bbab96058398dcc6803f7
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Thu Mar 7 04:19:21 2019 +0000
panfrost: Delay color buffer setup
In an effort to cleanup framebuffer management code, we delay
colour buffer setup until the FRAGMENT job is actually emitted, allowing
the AFBC and linear codepaths to be unified.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.visozo at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=536bcaa68ffb2b6f939cda4477929f5c3ff55a8c
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Thu Mar 7 03:52:20 2019 +0000
panfrost: Combine has_afbc/tiled in layout enum
AFBC, tiled, and linear BO layouts are mutually exclusive; they should
be coupled via a single enum rather than ad hoc checks of booleans.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.visozo at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d93c5c314882ea2d5befb6cb14bc8062e57dc703
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Thu Mar 7 03:24:45 2019 +0000
panfrost: Cleanup needless if in create_bo
I'm not sure why we were checking for these additional criteria (likely
inherited from some other driver); remove the needless checks to cleanup
the code and perhaps fix some bugs down the line.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.visozo at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1467deb5432a512845fb646ed7b44a2e2d36dbd6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 16 23:47:43 2017 -0800
i965: Reimplement all the PIPE_CONTROL rules.
This implements virtually all documented PIPE_CONTROL restrictions
in a centralized helper. You now simply ask for the operations you
want, and the pipe control "brain" will figure out exactly what pipe
controls to emit to make that happen without tanking your system.
The hope is that this will fix some intermittent flushing issues as
well as GPU hangs. However, it also has a high risk of causing GPU
hangs and other regressions, as this is a particularly sensitive
area and poking the bear isn't always advisable.
Mark Janes noted that this patch helps with some GPU hangs on Icelake.
This does re-enable the VF Invalidate => Write Immediate workaround
on Gen8, which had been disabled (bug 103787) due to GPU hangs. The
old code did this workaround after another which would have added CS
stall bits, so it missed a workaround. The new code orders them
properly and appears to work.
v4: Don't pass "bo, offset, imm" to a recursive CS stall (caught by
Topi Pohjolainen), drop Gen10 workarounds that are unnecessary for
production hardware.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6af96d1bc18cc5af733ca80b11f4a23c414abe1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 1 15:55:51 2018 -0700
i965: Use genxml for emitting PIPE_CONTROL.
While this does add a bunch of boilerplate, it also protects us against
the hardware moving bits, or changing their meaning. For something as
finnicky as PIPE_CONTROL, the extra safety seems worth it.
We turn PIPE_CONTROL_* into an bitfield of arbitrary flags, and then
pack them appropriately.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c6f7124086ba6926e0b622c9d1a2c61fddcfb4f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 1 15:55:21 2018 -0700
i965: Rename ISP_DIS to INDIRECT_STATE_POINTERS_DISABLE.
Clearer name.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa139f0980053f2344c62bc8070d7b46d9cedfff
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 16 22:37:02 2017 -0800
i965: Move some genX infrastructure to genX_boilerplate.h.
This will let us make multiple genX_*.c files, without copy and pasting
all this boilerplate.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecb708fadaf60147cff597d36e0e4753c7ebdf40
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 8 15:50:58 2019 -0700
gallium/winsys/kms: fix incomplete type compilation failure
Fixes:
../src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c: In function ‘kms_sw_displaytarget_from_handle’:
../src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c:402:60: error: dereferencing pointer to incomplete type ‘const struct pipe_resource’
templ->format,
^
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=04544d852c457ac333e2d43adb7d42d8c9b80d4f
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 8 15:49:49 2019 -0700
drisw: fix incomplete type compilation failure
Fixes:
../src/gallium/winsys/sw/dri/dri_sw_winsys.c: In function ‘dri_sw_displaytarget_display’:
../src/gallium/winsys/sw/dri/dri_sw_winsys.c:255:39: error: dereferencing pointer to incomplete type ‘struct pipe_box’
offset = dri_sw_dt->stride * box->y;
^
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=45c6da5a48b52594ea7f116a56ce92481fbb964a
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 7 20:39:49 2019 -0700
docs: try to improve the Meson documentation (v2)
Add new Introduction and Advanced Usage sections.
Spell out a few more details, like "ninja install".
Improve the layout around example commands.
Fix grammatical errors and tighten up the text.
Explain the --prefix option.
v2: Remove language about 'ninja clean' and move link to Meson
information about separate build directories earlier in the page.
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=187a527ed762b10e6e3156c678fea7aab0789157
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 6 16:20:55 2019 -0700
st/mesa: minor refactoring of texture/sampler delete code
Rename st_texture_free_sampler_views() to
st_delete_texture_sampler_views() to align with
st_DeleteTextureObject(), its only caller.
Move the call to st_texture_release_all_sampler_views() from
st_DeleteTextureObject() to st_delete_texture_sampler_views()
so all the sampler view clean-up code is in one place.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=70a2ede112acb589ee4310a0b3f7476fc1629b51
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 6 16:15:19 2019 -0700
st/mesa: rename st_texture_release_sampler_view()
To st_texture_release_context_sampler_view() to be more clear
that it's context-specific.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41adb3d6dff63d34e431972b37d304ff0a3070f1
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 6 16:09:09 2019 -0700
st/mesa: add/improve sampler view comments
Reviewed-by: Neha Bhende <bhenden at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7d25046254bbd1a96ce4ba7572c1afb8dc52afd
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 7 09:55:09 2019 -0700
st/mesa: move around some code in st_context.c
st_init_driver_functions() is only called in st_context.c so there's
no need for the prototype in st_context.h
To avoid a forward declaration of st_init_driver_functions() in
st_context.c, we need to move around several other functions.
No functional change.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b29d827f09729259d772c4bbbf1b4d4606359736
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 7 09:21:53 2019 -0700
st/mesa: move utility functions, macros into new st_util.h file
To de-clutter st_context.h.
Clean up remaining function prototypes in st_context.h.
The st_vp_uses_current_values() helper is only used in st_context.c
so move it there.
The st_get_active_states() function is only used in st_context.c so
remove its prototype in st_context.h
Reviewed-by: Neha Bhende <bhenden at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=775aabdd01739c413da7b38e5acbde1094209bcf
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date: Mon Mar 11 18:33:54 2019 +0100
anv: destroy descriptor sets when pool gets reset
As stated in Vulkan spec:
"Resetting a descriptor pool recycles all of the resources from all
of the descriptor sets allocated from the descriptor pool back to
the descriptor pool, and the descriptor sets are implicitly freed."
This fixes dEQP-VK.api.descriptor_pool.*
Fixes: 14f6275c92f1 "anv/descriptor_set: add reference counting for..."
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Tested-by: Clayton Craft <clayton.a.craft at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3235a942c16b61849bc16a710c53f0a7a5566f0d
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Dec 6 16:00:40 2018 +1100
nir: find induction/limit vars in iand instructions
This will be used to help find the trip count of loops that look
like the following:
while (a < x && i < 8) {
...
i++;
}
Where the NIR will end up looking something like this:
vec1 32 ssa_1 = load_const (0x00000004 /* 0.000000 */)
loop {
...
vec1 1 ssa_12 = ilt ssa_225, ssa_11
vec1 1 ssa_17 = ilt ssa_226, ssa_1
vec1 1 ssa_18 = iand ssa_12, ssa_17
vec1 1 ssa_19 = inot ssa_18
if ssa_19 {
...
break
} else {
...
}
}
On RADV this unrolls a bunch of loops in F1-2017 shaders.
Totals from affected shaders:
SGPRS: 4112 -> 4136 (0.58 %)
VGPRS: 4132 -> 4052 (-1.94 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 515444 -> 587720 (14.02 %) bytes
LDS: 2 -> 2 (0.00 %) blocks
Max Waves: 194 -> 196 (1.03 %)
Wait states: 0 -> 0 (0.00 %)
It also unrolls a couple of loops in shader-db on radeonsi.
Totals from affected shaders:
SGPRS: 128 -> 128 (0.00 %)
VGPRS: 64 -> 64 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 6880 -> 9504 (38.14 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 16 -> 16 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67c3478482f55a0e86397c0f1af65ccef84f089a
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Dec 6 15:56:55 2018 +1100
nir: pass nir_op to calculate_iterations()
Rather than getting this from the alu instruction this allows us
some flexibility. In the following pass we instead pass the
inverse op.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=11e8f8a166dad78985659214755f18f97da64545
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Dec 6 13:29:05 2018 +1100
nir: add get_induction_and_limit_vars() helper to loop analysis
This helps make find_trip_count() a little easier to follow but
will also be used by a following patch.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f219f6114ddbd43c239f22151b698bd1b5b7f86e
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Dec 6 11:17:45 2018 +1100
nir: add helper to return inversion op of a comparison
This will be used to help find the trip count of loops that look
like the following:
while (a < x && i < 8) {
...
i++;
}
Where the NIR will end up looking something like this:
vec1 32 ssa_1 = load_const (0x00000004 /* 0.000000 */)
loop {
...
vec1 1 ssa_12 = ilt ssa_225, ssa_11
vec1 1 ssa_17 = ilt ssa_226, ssa_1
vec1 1 ssa_18 = iand ssa_12, ssa_17
vec1 1 ssa_19 = inot ssa_18
if ssa_19 {
...
break
} else {
...
}
}
So in order to find the trip count we need to find the inverse of
ilt.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=090feaacdc83cdfa6a15485eac3a466489968841
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Dec 6 11:12:12 2018 +1100
nir: simplify the loop analysis trip count code a little
Here we create a helper is_supported_terminator_condition()
and use that rather than embedding all the trip count code
inside a switch.
The new helper will also be used in a following patch.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7571de8eaa50bca1e0162ce212c47a6f9e927120
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Tue Nov 20 15:23:45 2018 +1100
nir: unroll some loops with a variable limit
For some loops can have a single terminator but the exact trip
count is still unknown. For example:
for (int i = 0; i < imin(x, 4); i++)
...
Shader-db results radeonsi (all affected are from Tropico 5):
Totals from affected shaders:
SGPRS: 144 -> 152 (5.56 %)
VGPRS: 124 -> 108 (-12.90 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 5180 -> 6640 (28.19 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 17 -> 21 (23.53 %)
Wait states: 0 -> 0 (0.00 %)
Shader-db results i965 (SKL):
total loops in shared programs: 3808 -> 3802 (-0.16%)
loops in affected programs: 6 -> 0
helped: 6
HURT: 0
vkpipeline-db results RADV (Unrolls some Skyrim VR shaders):
Totals from affected shaders:
SGPRS: 304 -> 304 (0.00 %)
VGPRS: 296 -> 292 (-1.35 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 15756 -> 25884 (64.28 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 29 -> 29 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
v2: fix bug where last iteration would get optimised away by
mistake.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=68ce0ec22244726c1b61d91936a6b79ac20ab77a
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Tue Nov 20 13:45:58 2018 +1100
nir: calculate trip count for more loops
This adds support to loop analysis for loops where the induction
variable is compared to the result of min(variable, constant).
For example:
for (int i = 0; i < imin(x, 4); i++)
...
We add a new bool to the loop terminator struct in order to
differentiate terminators with this exit condition.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8a8937a04fd9531069616c63c099ba276296112
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Tue Nov 20 14:05:09 2018 +1100
nir: add partial loop unrolling support
This adds partial loop unrolling support and makes use of a
guessed trip count based on array access.
The code is written so that we could use partial unrolling
more generally, but for now it's only use when we have guessed
the trip count.
We use partial unrolling for this guessed trip count because its
possible any out of bounds array access doesn't otherwise affect
the shader e.g the stores/loads to/from the array are unused. So
we insert a copy of the loop in the innermost continue branch of
the unrolled loop. Later on its possible for nir_opt_dead_cf()
to then remove the loop in some cases.
A Renderdoc capture from the Rise of the Tomb Raider benchmark,
reports the following change in an affected compute shader:
GPU duration: 350 -> 325 microseconds
shader-db results radeonsi VEGA (NIR backend):
SGPRS: 1008 -> 816 (-19.05 %)
VGPRS: 684 -> 432 (-36.84 %)
Spilled SGPRs: 539 -> 0 (-100.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 39708 -> 45812 (15.37 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 105 -> 144 (37.14 %)
Wait states: 0 -> 0 (0.00 %)
shader-db results i965 SKL:
total instructions in shared programs: 13098265 -> 13103359 (0.04%)
instructions in affected programs: 5126 -> 10220 (99.38%)
helped: 0
HURT: 21
total cycles in shared programs: 332039949 -> 331985622 (-0.02%)
cycles in affected programs: 289252 -> 234925 (-18.78%)
helped: 12
HURT: 9
vkpipeline-db results VEGA:
Totals from affected shaders:
SGPRS: 184 -> 184 (0.00 %)
VGPRS: 448 -> 448 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 26076 -> 24428 (-6.32 %) bytes
LDS: 6 -> 6 (0.00 %) blocks
Max Waves: 5 -> 5 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fba5d275db178232ce52160d84757bd2fb1bd9b8
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Mon Nov 19 17:01:52 2018 +1100
nir: add new partially_unrolled bool to nir_loop
In order to stop continuously partially unrolling the same loop
we add the bool partially_unrolled to nir_loop, we add it here
rather than in nir_loop_info because nir_loop_info is only set
via loop analysis and is intended to be cleared before each
analysis. Also nir_loop_info is never cloned.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03a452b7d099b1d12b702a6d321431dbf039141b
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Nov 15 23:23:09 2018 +1100
nir: add guess trip count support to loop analysis
This detects an induction variable used as an array index to guess
the trip count of the loop. This enables us to do a partial
unroll of the loop, which can eventually result in the loop being
eliminated.
v2: check if the induction var is used to index more than a single
array and if so get the size of the smallest array.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=97f2d04d5eb93731700c1941c811bb354d057cfc
Author: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Date: Fri Mar 8 15:24:57 2019 +0100
panfrost: Add support for PAN_MESA_DEBUG
Signed-off-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0b1bbebdd9023dbb86313cbfac14cef3e6dca36
Author: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Date: Fri Mar 8 15:04:50 2019 +0100
panfrost/midgard: Add support for MIDGARD_MESA_DEBUG
Signed-off-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5236fc6e299225a94234ea5e381679ffbd36227
Author: Xavier Bouchoux <xavierb at gmail.com>
Date: Mon Oct 15 16:24:29 2018 +0200
nir/spirv: Fix assert when unsampled OpTypeImage has unknown 'Depth'
'dxc' hlsl-to-spirv compiler appears to emit 2 (Unknown) in the depth field,
when the image is not sampled and the value is not needed.
Previously, shaders failed with:
SPIR-V parsing FAILED:
In file ../src/compiler/spirv/spirv_to_nir.c:1412
!is_shadow
632 bytes into the SPIR-V binary
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d75f84cb6521c323092f50af41bce435d515a647
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Mar 9 01:02:06 2019 -0800
iris: Fix write enable in pinning of depth/stencil resources
We may bind new Z/S buffers (which come via the framebuffer CSO,
triggering IRIS_DIRTY_DEPTH_BUFFER), but with writes disabled.
The next draw may enable Z or S writes (which come via the ZSA CSO,
triggering IRIS_DIRTY_WM_DEPTH_STENCIL), which requires us to update
our pin to have the write flag.
So, update pinning if either dirty flag changes. To clarify, pass
cso_zsa to the pinning function rather than pulling the random values
out of ice->state, which unfortunately have to exist for the resolve
code since iris_depth_stencil_alpha_state only exists in iris_state.c.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=863e810a19d31cab58f4a7e579306ce1f8f2d16f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Mar 9 00:50:24 2019 -0800
iris: Refactor depth/stencil buffer pinning into a helper.
This avoids the code duplication that caused me to put things in the
wrong place in the previous commit. One used to have extra flushes,
but we moved those out so now these are identical and can be easily
shared.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9302414f8b0e4d767b6435290ddb8d349f3ab12f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Mar 9 00:42:54 2019 -0800
iris: Move depth/stencil flushes so they actually do something
Commit d6dd57d43cd (iris: Add missing depth cache flushes) added the
depth/stencil flushes to the wrong place. I meant to add them to the
iris_upload_dirty_render_state code that emits the packets, but I
accidentally added them to the nearly identical looking code in
iris_restore_render_saved_bos. This meant we missed the actual flushing
at draw time, but instead did pointless flushing on the first draw in a
batch where things are already flushed anyway.
This commit moves them to iris_resolve.c, next to the depth prepares,
similar to what we do for color buffers. i965 does them elsewhere, but
I'm not sure why - this seems like the most consistent place.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=076a7095bb46cd11ac1938be1652f5fdf862467b
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Tue Feb 26 18:41:07 2019 +0100
st/dri: allow direct UYVY import
Push this format to the pipe driver unchanged.
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=04ff2e3fbbb981606aa4d469316f6f00cc8083db
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 7 20:14:59 2019 -0800
iris: Fix TES gl_PatchVerticesIn handling.
1. If we switch the TCS for one with a different number of output
vertices, then the TES's gl_PatchVerticesIn value will change.
We need to re-upload in this case. For now, re-emit constants
whenever the TCS/TES are swapped out.
2. If there is no TCS, then we can't grab gl_PatchVerticesIn from
the TCS info. Since it's a passthrough, we can just use the
primitive's patch count (like the TCS gl_PatchVerticesIn does).
Fixes KHR-GL45.tessellation_shader.single.max_patch_vertices and
KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f51cb5e67524d55508ec7bc1ee2a9d4d1087291
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 6 20:56:37 2019 -0800
iris: Rework default tessellation level uploads
Now that we've added a system value uploading mechanism, we may as well
reuse the same system for default tessellation levels. This simplifies
the state upload code a bit.
Also fixes:
KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_tessLevel
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd5075e0594ba13c24eb195e098a814c8e76249b
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Thu Feb 14 00:28:20 2019 +0200
iris: Face should be a system value.
This patch adds PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL which
despite its name is not a TGSI-specific capability, just lets
the state tracker know that it should generate a system value
for FACE.
This is needed if we want to run tgsi_to_nir on iris.
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a9e2d608563d6d305c63039396644f3b976a55d
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 28 12:02:58 2019 -0800
vc4: Switch the post-RA scheduler over to the DAG datastructure.
Just a small code reduction from shared infrastructure.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33886474d646134f9784771a0ded3510a0180515
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 28 10:42:05 2019 -0800
v3d: Use the DAG datastructure for QPU instruction scheduling.
Just a small code reduction from shared infrastructure.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6d83b34ee3486d2154c1c929900d329448cb6c0
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 28 11:02:25 2019 -0800
vc4: Reuse list_for_each_entry_rev().
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c01ddbf7f1a543475e42a9854f0e3c60391012b
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 28 11:01:57 2019 -0800
v3d: Reuse list_for_each_entry_rev().
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a727c1a1204e904b9e13d145ac0e9db33675273
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 28 10:06:27 2019 -0800
vc4: Switch over to using the DAG datastructure for QIR scheduling.
Just a small code reduction from shared infrastructure.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0533d2d95c0df559e78de3bfeb8e8ae5b7fc8140
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 27 11:12:59 2019 -0800
util: Add a DAG datastructure.
I keep writing this for various schedulers.
Acked-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f0a922c277639abfd03c27c160b327a7889162b
Author: Kristian H. Kristensen <hoegsberg at chromium.org>
Date: Fri Mar 1 14:33:36 2019 -0800
freedreno/a6xx: Remove extra parens
There's a warning about this now.
Signed-off-by: Kristian H. Kristensen <hoegsberg at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08c452bef7db5121b41ad781a3ec1b8a550006da
Author: Kristian H. Kristensen <hoegsberg at chromium.org>
Date: Fri Mar 1 14:25:57 2019 -0800
freedreno: Use c_vis_args and no_override_init_args
Signed-off-by: Kristian H. Kristensen <hoegsberg at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=24af64baa531f9ac490bc5de433b2b2b52a3ccee
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 8 13:45:53 2019 -0800
turnip: preliminary support for Wayland WSI
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae82b5df88b9b307c2b7ce6f0f9b59332c83e362
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Feb 11 11:12:32 2019 -0800
turnip: preliminary support for tu_GetImageSubresourceLayout
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cb5fd0d7163a2430f14686faad037912f18b557
Author: Chad Versace <chadversary at chromium.org>
Date: Fri Feb 1 17:08:51 2019 -0800
turnip: Use Vulkan 1.1 names instead of KHR
That is, drop KHR from all tokens that were promoted to Vulkan 1.1.
The consistency makes ctags more useful (it now jumps directly to the
real definitions in vulkan_core.h instead of the typedefs); and it makes
the code slightly less verbose.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f863dc0f72719603a6fd60a62a1d619ee2696af
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 8 11:27:50 2019 -0800
turnip: guard -Dvulkan-driver=freedreno
Require -DI-love-half-baked-turnips=true as well to enable freedreno
vulkan driver.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=949ce2745d9006efab131cf3c447328143f23241
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 22 08:50:58 2019 -0800
turnip: preliminary support for tu_CmdDraw
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9b34622cd00e1738637b31b0b2a93f10c201b92
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 21 22:37:34 2019 -0800
turnip: preliminary support for draw state binding
This adds support for tu_CmdBindPipeline, tu_CmdBindVertexBuffers,
etc.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54b7a57c22c8de54ae1fbd659ac141a8802eb301
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Feb 20 14:26:06 2019 -0800
turnip: add draw_cs to tu_cmd_buffer
It will hold draw commands.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cdbab016ec7a47bcde6361920bfc26c366a6a46
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 21 22:31:36 2019 -0800
turnip: parse VkPipelineVertexInputStateCreateInfo
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d17096b9b1282d2205d1fc34c5331cdd0260c96a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 26 22:10:34 2019 -0800
turnip: parse VkPipelineShaderStageCreateInfo
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7d842c97c9803d7003a9a9d6e85097df5aeb0fc
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 26 22:09:37 2019 -0800
turnip: compile VkPipelineShaderStageCreateInfo
Compile all shaders and upload the binaries to a BO.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=970a8fec96440dc749d309505dfa17e8db028484
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Feb 20 09:53:47 2019 -0800
turnip: preliminary support for shader modules
Save SPIR-V in tu_shader_module. Tranlation to NIR happens in
tu_shader_create, and compilation to binary code happens in
tu_shader_compile. Both will be called during pipeline creation.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e0d87878735ee65b8b5529640bc18139d0b7b9f
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 21 14:58:52 2019 -0800
turnip: parse VkPipeline{Multisample,ColorBlend}StateCreateInfo
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bec0abf294d704c8a5d555ef0548cdc7a100a7d0
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 21 11:46:59 2019 -0800
turnip: parse VkPipelineDepthStencilStateCreateInfo
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9496b377ffe05c0e2abd79fd8158f2ef0d81eb9a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 26 23:29:51 2019 -0800
turnip: parse VkPipelineRasterizationStateCreateInfo
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4884761e8d85225bcf53d87e6d3bf2572af30c8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 19 13:49:01 2019 -0800
turnip: parse VkPipelineViewportStateCreateInfo
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bea6a91cb3d8498c8a7e6985be3585cac94f20a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 21 11:07:38 2019 -0800
turnip: parse VkPipelineInputAssemblyStateCreateInfo
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c584c2e86c3889e39d1f3be71fcefa18a8a5f6ae
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 21 09:41:49 2019 -0800
turnip: parse VkPipelineDynamicStateCreateInfo
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=df48cb7b3edc03e547b03f2994f13428012a02df
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 21 09:22:17 2019 -0800
turnip: create a less dummy pipeline
Still dummy, but at least it is created from tu_pipeline_builder.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=57327626dc754be46841997c5c2f777e7f326c40
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Feb 25 14:38:34 2019 -0800
turnip: simplify tu_cs sub-streams usage
Let tu_cs_begin_sub_stream imply tu_cs_reserve_space, and
tu_cs_end_sub_stream imply tu_cs_sanity_check. Callers are no
longer required to call them (but can still do if they choose to).
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59419bb691b2ba6af55146004bf876e7c7face82
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Feb 25 14:37:55 2019 -0800
turnip: fix tu_cs sub-streams
Update cs->start in tu_cs_end_sub_stream. Otherwise, the entry
would include commands from all prior sub-streams.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0567e84dbbcac5ef52ddd472be2f5bc1e8cdc69
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Feb 25 14:57:03 2019 -0800
turnip: tu_cs_emit_array
Array version of tu_cs_emit. Useful for updating multiple
consecutive array-like registers, or loading a shader binary with
SS6_DIRECT.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fffaa9b4b36be4abdecefd4578ca685da57ed3e2
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Feb 25 14:49:34 2019 -0800
turnip: add tu_cs_discard_entries
We will start a draw IB at the beginning of a subpass and consume it
at the end of the subpass. With tu_cs_discard_entries, we can reuse
the same tu_cs for all subpasses.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=10c50134422ae166fccfe4fbf4961407b63d20f5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Feb 25 14:55:06 2019 -0800
turnip: more/better asserts for tu_cs
Asserting (cur < end) in tu_cs_emit catches much less programming
errors comparing to asserting (cur < reserved_end). We should never
write more commands than what we have reserved.
Assert IB is non-empty and sane in tu_cs_emit_ib.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa7dd6cb7f54180af91e40e38bf8890c5cc12197
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Feb 25 14:44:52 2019 -0800
turnip: use 32-bit offset in tu_cs_entry
We don't support nor expect BOs to be that big in tu_cs.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8a5e10d0d6e6cb79417cf10ef09474eb8d8fc4e
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Feb 25 14:32:36 2019 -0800
turnip: mark IBs for dumping
Includes IBs in kernel cmdbuf dumps.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a48dd9fb8ffef3f90dbf4538f8a17d4e239f997
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 12:31:06 2019 +0000
turnip: use the platform defines in vk.xml instead of hard-coding them
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d12bcbfa7a97823ec55f885613b79a070dee95f
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Feb 21 22:39:22 2019 +0100
turnip: Add todo for copies.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=51115e7201987c93f805fe590678f4978aee8baf
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Mon Feb 18 16:43:24 2019 +0100
turnip: Add buffer->image DMA copies.
Passes dEQP-VK.api.copy_and_blit.core.buffer_to_image.*
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66165634724abc9c1a0249411667045d44d2830f
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Mon Feb 18 16:13:23 2019 +0100
turnip: Add image->buffer DMA copies.
Passes dEQP-VK.api.copy_and_blit.core.image_to_buffer.*
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d76a1e2aa17fabfa6e6fac44e044a48c02c63875
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Mon Feb 18 16:09:27 2019 +0100
turnip: Implement buffer->buffer DMA copies.
Passes dEQP-VK.api.copy_and_blit.core.buffer_to_buffer.*
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bafbf3bafe4440e61b5ba97716de5b270a2be9d8
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Mon Feb 4 14:52:34 2019 +0100
turnip: Add tu6_rb_fmt_to_ifmt.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=148876d424cb26ad28f0a3333792da3558a39ac9
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Mon Feb 18 14:49:52 2019 +0100
turnip: Make tu6_emit_event_write shared.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=72384715873f3b7d5a4403e2381d8fbd896c891c
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Tue Jan 15 22:54:15 2019 +0100
turnip: Add buffer memory binding.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08b1c3fc7f1c5ea5b5bee1eccb635b855c4f383b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 14 10:53:20 2019 -0800
turnip: respect color attachment formats
Make tu6_get_native_format available to tu_cmd_buffer and start
using of it.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=68c27ea92b92e4d8ba6a687523975ac383adb836
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Feb 14 14:36:52 2019 -0800
turnip: preliminary support for fences
This should be quite complete feature-wise. External fences are
still missing. We probably also want to add a simpler path to
tu_WaitForFences for when fenceCount == 1.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15319963fa45ae3fa8b6a097fa9ed0b8751807cc
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Feb 13 10:23:32 2019 -0800
turnip: fix VkClearValue packing
Add tu_pack_clear_value to correctly pack VkClearValue according to
VkFormat. It ignores the component order defined by VkFormat, and
always packs to WZYX order.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6545461041c42022cc66811205339098b4c6973b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 1 10:36:19 2019 -0800
turnip: add support for VK_KHR_external_memory_{fd,dma_buf}
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d1c4049de8038ca16bb76aefd66b70d29f2841d
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 1 10:27:28 2019 -0800
turnip: advertise VK_KHR_external_memory
AFAICT, it is supported. We don't need to handle any of the new
structs because our BOs can always be exported.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=025384527215a023bf6c035e0e8c6b1a92ddaa13
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 1 10:12:38 2019 -0800
turnip: advertise VK_KHR_external_memory_capabilities
AFAICT, it is supported.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de89436216e178b616aa3969e3d68b24b60602fd
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 31 15:03:03 2019 -0800
turnip: add functions to import/export prime fd
Add tu_bo_init_dmabuf, tu_bo_export_dmabuf, tu_gem_import_dmabuf,
and tu_gem_export_dmabuf.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5239bc59c328a04d8cc44dabbacfe9a4c973ba9
Author: Chad Versace <chadversary at chromium.org>
Date: Fri Feb 1 16:48:44 2019 -0800
turnip: Fix error behavior for VkPhysicalDeviceExternalImageFormatInfo
If the handle type is unsupported, then the spec requires us to return
VK_ERROR_FORMAT_NOT_SUPPORTED.
Reviewed-by: Chia-I Wu <olvaffe at gmail.com>
Closes: https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/merge_requests/17
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b9f967cd1a95c3fe577eb4296b8d6eb017daa15
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 25 11:13:54 2019 -0800
turnip: add a more complete format table
A format table is an array of tu_native_format. Table lookup is
done through array indexing.
This commit defines a single format table for core VkFormat. It is
derived from the table in the gallium driver. There might be errors
introduced in the process of the conversion.
When an extension that defines new VkFormat is supported, we need to
add a new table for the extension.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3bf77918452062d0044771e3fa5af0105aa5cee
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 11 15:01:26 2019 -0800
turnip: preliminary support for loadOp and storeOp
- create tile_load_ib and tile_store_ib at the beginning of each
subpass
- execute the IBs at the end of each subpass
- no DONT_CARE support
- no subpass dependency analysis and subpass merging
- no zs support
- no true VkImageView support
- assume VK_FORMAT_B8G8R8A8_UNORM
- no tiling
- no MSAA
This also removes cur_cs from tu_cmd_buffer.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0aeef7c8bd5917633392decce1c07ff36c652cc1
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 29 15:00:34 2019 -0800
turnip: add TU_CS_MODE_SUB_STREAM
When in TU_CS_MODE_SUB_STREAM, tu_cs_begin_sub_stream (or
tu_cs_end_sub_stream) should be called instead of tu_cs_begin (or
tu_cs_end). It gives the caller a TU_CS_MODE_EXTERNAL cs to emit
commands to.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f59c3814232d5735aba6bed9de506e59321e4170
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 28 14:33:20 2019 -0800
turnip: add tu_cs_mode
Add tu_cs_mode and TU_CS_MODE_EXTERNAL. When in
TU_CS_MODE_EXTERNAL, tu_cs wraps an external buffer and can not
grow.
This also moves tu_cs* up in tu_private.h, such that other structs
can embed tu_cs_entry.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c63fc626f98def10d20971161e672f9e7cd341c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 29 10:43:48 2019 -0800
turnip: provide both emit_ib and emit_call
tu_cs_emit_ib emits a CP_INDIRECT_BUFFER for a BO. tu_cs_emit_call
emits a CP_INDIRECT_BUFFER for each entry of a target cs.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=741a4325df3a9c605bf85d2429f4af97a755e407
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 28 16:31:54 2019 -0800
turnip: add tu_cs_sanity_check
It replaces tu_cs_reserve_space_assert and can be called at any
time to sanity check tu_cs.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=29f111000399821452e8538ca74ce2de7210ee47
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 28 15:55:40 2019 -0800
turnip: never fail tu_cs_begin/tu_cs_end
Error checking tu_cs_begin/tu_cs_end is too tedious for the callers.
Move tu_cs_add_bo and tu_cs_reserve_entry to tu_cs_reserve_space
such that tu_cs_begin/tu_cs_end never fails.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d81be3959234c3d877efd6ddee5280b01815433
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 28 16:24:48 2019 -0800
turnip: specify initial size in tu_cs_init
We will drop size parameter from tu_cs_begin shortly, such that
tu_cs_begin never fails.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2774a1b97d450c81108c4f8d00c948d8e3427c4f
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 28 15:52:36 2019 -0800
turnip: add tu_cs_{reserve,add}_entry
We will stop calling tu_cs_reserve_entry in tu_cs_end shortly, such
that tu_cs_end never fails.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c11580373f15e36fd6c235b62915ce9f90af8feb
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 29 14:09:17 2019 -0800
turnip: add internal helpers for tu_cs
Add tu_cs_get_offset, tu_cs_get_size, tu_cs_get_space, and
tu_cs_is_empty.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=429e2d5755ea8fe2cf9db82b01262a248a0d2671
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 22 10:27:22 2019 -0800
turnip: add tu_tiling_config
We need the current color/depth/stencil attachments and the current
render area to compute the tiling config.
We compute the tiling config at the beginning of each subpass for
the moment. We should change that when the driver can reorder/merge
subpasses.
It is very common that the render area is the entire framebuffer.
We might want to optimize for the case and compute the tiling config
in tu_framebuffer ctor.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c4483de0ee7b46981dab0459d222774524db461
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 22 10:27:18 2019 -0800
turnip: preliminary support for tu_GetRenderAreaGranularity
Set it to tile alignments, 32x32 on 6xx.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c83a7572b22c907cb41107cd991ec4fcea216cf
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 18 08:54:04 2019 -0800
turnip: emit HW init in tu_BeginCommandBuffer
Being the first commit that emits meaningful command packets, there
are many things included in this commit
- tu6_emit_xxx are low-level helpers that emit command packets
without boundary checks
- tu6_xxx are high-level helpers that emit command packets with
boundary checks
- cmdbuf->cs is a pointer to the current CS, so that we can use the
helpers above to emit to other CS
- use cmd as the variable name of tu_cmd_buffer
- there is a per-cmdbuf scratch bo for CP_EVENT_WRITE writeback
- there is a per-cmdbuf debug marker, using scratch reg 7 or 6
depending on whether the cmdbuf is primary or secondary
(olv, after rebase) REG_A6XX_SP_UNKNOWN_AB20 is renamed
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b3af6321b9231752014ed441ba9b056219e23aa
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 18 14:24:45 2019 -0800
turnip: add tu_cs_reserve_space(_assert)
They are used like
tu_cs_reserve_space(...);
tu_cs_emit(...);
...;
tu_cs_reserve_space_assert();
to make sure we reserved enough space at the beginning.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aaa59ef70c100fe861c099197581a1131f2bc8a4
Author: Chad Versace <chadversary at chromium.org>
Date: Wed Jan 16 15:01:35 2019 -0800
turnip: Annotate vkGetImageSubresourceLayout with tu_stub
Reviewed-by: Chia-I Wu <olvaffe at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba6bcb387cc1e693d85bc11dde3913b4f9133d67
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 11 14:27:01 2019 -0800
turnip: preliminary support for tu_CmdBeginRenderPass
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1085df8176cbc18c5ad59bed3906e27c26ab1766
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 10 11:58:07 2019 -0800
turnip: preliminary support for tu_image_view_init
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=992ecdd40ebc2e027b39f98a92bdab953eedd5d5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 10 11:51:39 2019 -0800
turnip: preliminary support for tu_BindImageMemory2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef49b07b83dc527dfdeb7ac9252c853cb67b086b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 17 11:15:39 2019 -0800
turnip: add cmdbuf->bo_list to bo_list in queue submit
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c4df43db591367aa2766cec399da1c657245a93
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 17 11:15:21 2019 -0800
turnip: add tu_bo_list_merge
tu_bo_list_merge adds an entire list to the current list.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ad01913bd2122c108a51a32aa40cc2b23aed768
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 17 10:23:19 2019 -0800
turnip: build drm_msm_gem_submit_bo array directly
Build drm_msm_gem_submit_bo array directly in tu_bo_list. We might
change this again, but this is good enough for now.
There are other issues as well, such as not using
VkAllocationCallbacks and sloppy error checking. We should revisit
this in the near future. Same to tu_cs.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c969d8b975072221adc898a34cf9bc5be8ab3402
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 16 14:40:37 2019 -0800
turnip: add more tu_cs helpers
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=39ba2b20d112c6235d89683a68314a48fb5571f4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 16 14:12:53 2019 -0800
turnip: inline tu_cs_check_space
This allows the fast path (size check) to be inlined.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bcaa78236447dd696888b9da67103af74c42bc4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 16 14:05:55 2019 -0800
turnip: update cs->start in tu_cs_end
This allows us to assert that there is no dangling command in
tu_cs_begin, rather than discarding them silently.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b01d1618a4d5d3802dce9cfafee072353566a9a8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 16 14:00:43 2019 -0800
turnip: minor cleanup to tu_cs_end
Add comments and error checking.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=af4eb208916d0fc2aecf1a0a44bc29cf49441a84
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 16 11:17:26 2019 -0800
turnip: add tu_cs_add_bo
Refactor BO allocation code out of tu_cs_begin. Add error checking.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae9a72b48b4fe77113d12a5de0cdb5a0746b8d0a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 16 10:20:33 2019 -0800
turnip: document tu_cs
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=45120127ea3775e4f4f42f8776a72b4d5f423329
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 16 10:03:02 2019 -0800
turnip: run sed and clang-format on tu_cs
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0801019d335c6584716cb99fc7b8ca42cc0064b0
Author: Kristian H. Kristensen <hoegsberg at chromium.org>
Date: Wed Jan 16 11:02:38 2019 -0800
turnip: Only get bo offset when we need to mmap
The offset we get from MSM_INFO_GET_OFFSET is an offset into the drm fd
for the purpose of mmaping the buffer.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23d6f0f9700d326f135f6d927b23563c9fd98acc
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Wed Jan 16 18:27:04 2019 +0100
turnip: Move stream functions to tu_cs.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac2a845abf4edf3419acc1dec5601cbe2ea7782b
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Tue Jan 15 22:18:15 2019 +0100
turnip: Add emit functions in a header.
This adds a radv-style check_space functions + emit functions.
Also puts them in a header as a bunch of inlines, so
(1) we can use them from meta code.
(2) they are inline for performance as these are common and small.
Did not put them in tu_private.h as a bunch of inlines only
clutters up that huge headerfile.
Precise error propagation for memory allocation failures is still
todo.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e684cb80000f5e615524f538358e0321d18e3e8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 10 14:07:50 2019 -0800
turnip: preliminary support for tu_QueueWaitIdle
This creates a new fd on each queue submit. I do not go with
DRM_IOCTL_MSM_WAIT_FENCE solely because the path is marked legacy.
Otherwise, we can use the fence id rather than requesting a fence
fd until external fences are supported and enabled.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7a6a80e6c66b8bb91dcadd9a868c46fc138b26b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 11 10:55:15 2019 -0800
turnip: constify tu_device in tu_gem_*
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3809e6cf638936642c1b2aff00d3354a5962afb3
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 10 15:34:44 2019 -0800
turnip: add wrappers around DRM_MSM_SUBMITQUEUE_*
Add tu_drm_submitqueue_new and tu_drm_submitqueue_close.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcf24f47aac414cbd634be5085002a5698618678
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jan 10 15:27:28 2019 -0800
turnip: add wrappers around DRM_MSM_GET_PARAM
Add tu_drm_get_gpu_id and tu_drm_get_gmem_size.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a25a803127c5f59ce9049d22c85e5dd7771014f6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 11 10:09:53 2019 -0800
turnip: remove unnecessary libfreedreno_drm dep
Remove libfreedreno_drm dep and unused fd_device.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=91232c52fe49848aa622a31e38e5ba0d008d08e0
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 11 10:03:51 2019 -0800
turnip: use msm_drm.h from inc_freedreno
The recent change to msm_drm.h changed the APIs in an incompatible
way.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f32869e3dcd70f25e828d1e337e027c5980032b
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Jan 10 22:07:04 2019 +0100
turnip: Shorten primary_cmd_stream name.
It really is too long.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=26261847cfcea3562d7eda04d2cdf883eb55d3d3
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Jan 10 21:39:14 2019 +0100
turnip: Fill command buffer
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=abe352525d032cd17b441ed73b4315f350cb2177
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Jan 10 21:25:20 2019 +0100
turnip: Implement submission.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=abf0792bbeaa96212963ba7c53ddb85c33a1b46a
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Jan 10 21:20:35 2019 +0100
turnip: Make bo_list functions not static
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=65e0e790548d3ef65f26d0fc6b1b370d93c577fb
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Jan 10 21:12:38 2019 +0100
turnip: Add msm queue support.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=871349965753ae7df897e2db488f22743b1bf1c5
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Mon Dec 31 14:15:30 2018 +0100
turnip: Add a command stream.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3a9b0792325f849246baab73cf19c51f2238122
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Mon Dec 31 11:34:32 2018 +0100
turnip: Implement a slow bo list
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=48b65201a6cf7a0b93dad94b4986c5dfc49c69ef
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Mon Dec 31 11:08:45 2018 +0100
turnip: Implement some UUIDs.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ae005f0370955f9b8d6e179a13593448800a93b
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Dec 28 17:27:12 2018 +0100
turnip: clean up TODO.
./deqp-vk -n dEQP-VK.info.*
Writing test log into TestResults.qpa
dEQP Core unknown (0xcafebabe) starting..
target implementation = 'Surfaceless'
WARNING: tu is not a conformant vulkan implementation, testing use only.
WARNING: tu is not a conformant vulkan implementation, testing use only.
Test case 'dEQP-VK.info.build'..
Pass (Not validated)
Test case 'dEQP-VK.info.device'..
Pass (Not validated)
Test case 'dEQP-VK.info.platform'..
Pass (Not validated)
Test case 'dEQP-VK.info.memory_limits'..
Pass (Pass)
DONE!
Test run totals:
Passed: 4/4 (100.0%)
Failed: 0/4 (0.0%)
Not supported: 0/4 (0.0%)
Warnings: 0/4 (0.0%)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=06602bf77f8f813c7be914617193b7fa9c472524
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Dec 28 17:25:17 2018 +0100
turnip: Remove some radv leftovers.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c72e6085e7bb466fb9c00204a21b7f0bccc0db38
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Dec 28 16:27:24 2018 +0100
turnip: Implement some format properties for RGBA8.
Just to get some tests to not skip. This is neither complete
nor completely correct.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d30baaaba645dcc1b4b4e16c4914554b896ea54a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 9 14:16:01 2019 -0800
turnip: add .clang-format
Add and apply .clang-format.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6401ad389e9cec6f523e4e4e989c190fb25a8dfc
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Dec 21 14:49:30 2018 +0100
turnip: Implement pipe-less param query.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0562e272f8a2a41d0639b65a5158b0c3b2dfd3b
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Dec 21 14:12:17 2018 +0100
turnip: move tu_gem.c to tu_drm.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d99dd55a04dd91af96d647d98d525df8ff7deda
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Dec 21 13:46:06 2018 +0100
turnip: Stop hardcoding the msm version check.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9c3dc8ec8ac1deb7b62f6e43b17bca7a2d7a290
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Dec 21 12:50:55 2018 +0100
turnip: Add image layout calculations.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=603354cffa8d98c049ff20567164061e8a4fec17
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Dec 21 00:54:15 2018 +0100
turnip: Fix memory mapping.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=426f6e46a80a12fdb47ab04cd657ddc28bf1d60d
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Dec 20 22:57:07 2018 +0100
turnip: Fix bo allocation after we stopped using libdrm_freedreno ...
Al this figuring out new errors is why I don't like reinventing the
wheel.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0a24e123faf3e3ad9db1146b2fc2082072030c8
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Dec 20 18:08:49 2018 +0100
turnip: Add 630 to the list.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3b5eea2cc7592219d6b4e7f4aea06846266bad8
Author: Chad Versace <chadversary at chromium.org>
Date: Mon Nov 12 14:45:47 2018 -0800
turnip: Don't return from tu_stub funcs
Since the macros are lowercase and look like normal functions, that they
change control flow with a hidden return is surprising.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf709dfe3f82a1b58e8d332bce7770ae4b72f6c1
Author: Chad Versace <chadversary at chromium.org>
Date: Mon Nov 12 14:42:36 2018 -0800
turnip: Fix 'unused' warnings
Now turnip builds without warnings on my machine.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=471f2d8409a4bc76e849f6d86639a2cef21d9e2f
Author: Chad Versace <chadversary at chromium.org>
Date: Mon Nov 12 14:28:58 2018 -0800
turnip: Add TODO file
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=359e9016c56103614f36b80b47ee16e5cffeade6
Author: Chad Versace <chadversary at chromium.org>
Date: Tue Nov 6 21:26:45 2018 -0700
turnip: Replace fd_bo with tu_bo
(olv, after rebase) remove inc_drm_uapi
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb16ec715f12d2f1723e5a0677664b8cc55a26b3
Author: Chad Versace <chadversary at chromium.org>
Date: Mon Nov 12 14:21:45 2018 -0800
turnip: Use vk_errorf() for initialization error messages
This small cleanup better prepares turnip for VK_EXT_debug_report.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1372c95ad26da146454108b7fc44488f28fe91bb
Author: Chad Versace <chadversary at chromium.org>
Date: Mon Nov 12 14:23:42 2018 -0800
turnip: Add TODO for Android logging
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cca208a0330f72d1cba7f679cf78e1121ee23d7b
Author: Chad Versace <chadversary at chromium.org>
Date: Mon Nov 12 14:13:13 2018 -0800
turnip: Require DRM device version >= 1.3
Because the driver will require support for iova.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5486943ed969ff421c7d4ab7fa35104bff668d74
Author: Chad Versace <chadversary at chromium.org>
Date: Tue Nov 6 22:14:04 2018 -0700
turnip: Fix indentation
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=99a5de14cbde2a5b66b2f1240cb17210b838e469
Author: Chad Versace <chadversary at chromium.org>
Date: Wed Nov 7 00:17:30 2018 -0700
turnip: Fix a real -Wmaybe-uninitialized
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75f2c8458b79916e5873a8554358d7953adb7bce
Author: Chad Versace <chadversary at chromium.org>
Date: Tue Nov 6 23:51:05 2018 -0700
turnip: Use vk_outarray in all relevant public functions
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ec87d56bd75e905d7ba99f4bdbf0e6e6015dd90
Author: Chad Versace <chadversary at chromium.org>
Date: Wed Nov 7 00:01:03 2018 -0700
turnip: Fix result of vkEnumerate*ExtensionProperties
Given an unsupported layer name, the functions must return
VK_ERROR_LAYER_NOT_PRESENT.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee835c779000134f62f2d01eba4693b6324c09e7
Author: Chad Versace <chadversary at chromium.org>
Date: Tue Nov 6 23:52:57 2018 -0700
turnip: Fix result of vkEnumerate*LayerProperties
The functions must not return VK_ERROR_LAYER_NOT_PRESENT. The spec
reserves that error for vkEnumerate*ExtensionProperties.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=daffb01704f5d570893195f9e71826c93d1e8961
Author: Chad Versace <chadversary at chromium.org>
Date: Sun Nov 4 23:42:55 2018 -0700
turnip: Fix indentation in function signatures
Due to s/anv/tu/, in many function signatures the indentation of
parameters was off-by-one.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4f3e0d5497d0726246da9d27697eeb2a1b71a15
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Fri Aug 17 14:48:46 2018 +0200
turnip: Disable more features.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a01edd9c86e54d734267c55b6ce56c23b0fc7082
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Fri Aug 17 14:43:01 2018 +0200
turnip: Initialize memory type in requirements.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7be2e1fc371979bd308d037cc8e45656b32b4bfd
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Fri Aug 17 14:35:59 2018 +0200
turnip: Cargo cult the Intel heap size functionality.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=462b693d943b8ba4cf80db9bc5238819ca798012
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Aug 10 13:30:08 2018 +0200
turnip: Report a memory type and heap.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e52e8183c2dec8bf0ef85284f8883dc392b7acd
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Fri Aug 10 13:19:22 2018 +0200
turnip: Add buffer allocation & mapping support.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0d62e4337e1bdbd918c4be997fed6b31c8a7e9e
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Aug 9 20:45:49 2018 +0200
turnip: Fix newly introduced warning.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcd15ab34e57b322f992c1b5292cfaefdb750cec
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Aug 9 11:14:33 2018 +0200
turnip: Remove abort.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13ff7ffbcb093f4ccbb9a1c00017034324f9af5e
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Aug 9 11:09:01 2018 +0200
turnip: Gather some device info.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7922d50bd4810c203226c70f10b43255e20317d4
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Thu Aug 9 10:36:06 2018 +0200
turnip: Fix up detection of device.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c63cb15745919acdd825e0676eb09664a772ef9c
Author: Chad Versace <chadversary at chromium.org>
Date: Sun Nov 4 22:27:54 2018 -0800
turnip: Drop Makefile.am and Android.mk
The Makefile.am doesn't work. I tried fixing it but gave up because
I don't understand Autotools. I strongly suspect the Android.mk also
doesn't work.
Rather than maintain the broken build files, let's delete them and
re-add working build files if-and-when we need them. (Maybe we'll be
lucky and turnip will never need to support Autotools!).
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=26380b3a9f8fd513dc4da86798f3c15191914fc2
Author: Bas Nieuwenhuizen <basni at chromium.org>
Date: Wed Aug 8 22:23:57 2018 +0000
turnip: Add driver skeleton (v2)
meson files have been updated, autotools and android still need
updating.
Only build tested.
v2 (chadv):
- Rebase onto master.
- Fix build breakage in Python scripts.
- Drop the WSI code. The internal WSI apis have changed recently, and
will likely change again before the driver goes upstream. To avoid
unnecessary rebase work, let's drop the WSI code and re-add it when
we're ready to really use WSI.
(olv, after rebase) do not enable freedreno by default on ARM
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d086d16b8165244db53f20dbf60c921f4bb38f38
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Mar 8 13:05:53 2019 +0100
nir/serialize: Prevent writing uninitialized state_slot data
The nir_state_slot struct had some padding that was never initialized.
Serializing the individual parts of the struct is more robust and avoids
the overhead of zeroing it at creation, so just do that.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=47fc359822494935852de1e70e4d840b2fe6a25c
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Mar 11 11:30:01 2019 +0200
anv: release memory allocated by glsl types during spirv_to_nir
Fixes leaks for each glsl_type generated:
==32470== 384 bytes in 3 blocks are possibly lost in loss record 18 of 18
==32470== at 0x483880B: malloc (vg_replace_malloc.c:309)
==32470== by 0x4C43F4A: ralloc_size (ralloc.c:119)
==32470== by 0x4C44014: rzalloc_size (ralloc.c:151)
==32470== by 0x4C44258: rzalloc_array_size (ralloc.c:215)
==32470== by 0x4D38957: glsl_type::glsl_type(glsl_struct_field const*, unsigned int, char const*) (glsl_types.cpp:114)
==32470== by 0x4D3BEED: glsl_type::get_struct_instance(glsl_struct_field const*, unsigned int, char const*) (glsl_types.cpp:1146)
==32470== by 0x4D42ECC: glsl_struct_type (nir_types.cpp:501)
==32470== by 0x4CDB5A1: vtn_handle_type (spirv_to_nir.c:1269)
==32470== by 0x4CE53DD: vtn_handle_variable_or_type_instruction (spirv_to_nir.c:4018)
==32470== by 0x4CD8CFF: vtn_foreach_instruction (spirv_to_nir.c:365)
==32470== by 0x4CE5E6B: spirv_to_nir (spirv_to_nir.c:4490)
==32470== by 0x497AF10: anv_shader_compile_to_nir (anv_pipeline.c:173)
v2: move release call to vkDestroyInstance
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9a6460bbff16abf337e1267c534da96035e7ac6
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Sun Nov 25 15:15:09 2018 +0000
wsi/x11: use WSI_FROM_HANDLE() instead of pointer casts
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2e24dd81d338421de63d66b0988fd4f0e72db8e
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Sun Oct 28 13:40:12 2018 +0000
wsi/wayland: fix pointer casting warning on 32bit
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=687babc04532a602937148c9e2ae31dd8daced9e
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Sun Oct 28 13:39:30 2018 +0000
wsi/display: s/#if/#ifdef/ to fix -Wundef
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ee01d91c7e9bb0922b112c11a374283e2ca454b
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Sun Oct 28 13:37:26 2018 +0000
wsi: deduplicate get_current_time() functions between display and x11
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bb34ecff9833e0b490e90ab04fdaa6342eadc1b
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Mar 8 10:29:26 2019 +0200
anv: release memory allocated by bo_heap when descriptor pool is destroyed
Fixes following leak:
==21853== 32 bytes in 1 blocks are definitely lost in loss record 2 of 20
==21853== at 0x483AB1A: calloc (vg_replace_malloc.c:762)
==21853== by 0x4C4DD7F: util_vma_heap_free (vma.c:221)
==21853== by 0x4C4D647: util_vma_heap_init (vma.c:46)
==21853== by 0x4957B9F: anv_CreateDescriptorPool (anv_descriptor_set.c:578)
Fixes: c520f4dec9cb ("anv: Add a concept of a descriptor buffer")
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=105002bd2d6173b24f6955c22340b5bc77e029fa
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Mar 4 14:22:36 2019 +0200
anv: destroy descriptor sets when pool gets destroyed
Patch maintains a list of sets in the pool and destroys possible
remaining sets when pool is destroyed.
As stated in Vulkan spec:
"When a pool is destroyed, all descriptor sets allocated from
the pool are implicitly freed and become invalid."
This fixes memory leaks spotted with valgrind:
==19622== 96 bytes in 1 blocks are definitely lost in loss record 2 of 3
==19622== at 0x483880B: malloc (vg_replace_malloc.c:309)
==19622== by 0x495B67E: default_alloc_func (anv_device.c:547)
==19622== by 0x4955E05: vk_alloc (vk_alloc.h:36)
==19622== by 0x4956A8F: anv_multialloc_alloc (anv_private.h:538)
==19622== by 0x4956A8F: anv_CreateDescriptorSetLayout (anv_descriptor_set.c:217)
Fixes: 14f6275c92f1 ("anv/descriptor_set: add reference counting for descriptor set layouts")
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=051b4064da5e28c13f691385c48d1d86e525774c
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Mon Feb 18 15:40:49 2019 +1100
anv: add support for dumping shader info via VK_EXT_debug_report
This information will be used by the vkpipeline-db tool.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f36794d1f0c7f3638f34ff6face8840938a445d0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Mar 9 00:25:30 2019 -0800
iris: Fix backface stencil write condition
A bit too much search and replace here.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea2cd73625950a56dffb1bfc009ae86c53545ce0
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Sun Mar 10 19:16:56 2019 +0000
panfrost/drm: Cast pointer to u64 to fix warning
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=756f7b99895404bc7d7ce0cfcd84044cc21a799f
Author: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Date: Fri Mar 8 10:27:07 2019 +0100
panfrost: Add backend targeting the DRM driver
This backend interacts with the new DRM driver for Midgard GPUs which is
currently in development.
When using this backend, Panfrost has roughly on-par functionality as
when using the non-DRM driver from Arm.
Alyssa Rosenzweig: To do so, we implement additional routines for
runtime GPU version detection and fencing. We cleanup some duplicate
code interfering with the new driver. We fix a long-standing memory leak
which is aggravated on the new driver. Finally, we implement BO
import/export in a way compatible with the new driver. These changes are
squashed to preserve bisectability given the hard-to-track ABI shifts in
the nondrm module
Signed-off-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4dc79df72e05346b4dd40d19e346ada9e4af98c
Author: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Date: Fri Mar 8 10:27:06 2019 +0100
panfrost: Add gem_handle to panfrost_memory and panfrost_bo
It will be used by the DRM backend to store GEM handles from the kernel.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=941adcef036c1a427c66ab08d041a008431c1e8c
Author: Rob Clark <robdclark at gmail.com>
Date: Sun Mar 10 11:08:10 2019 -0400
freedreno/a6xx: more bcolor fixes
Non-zero offset wasn't working, which breaks a bunch of
dEQP-GLES31.functional.texture.border_clamp.formats.* when doing sharded
deqp runs (because order of tests changes, resulting in different
texture state bound.. deqp doesn't really clean up it's gl state between
tests very well)
Previously, if additional textures were bound, due to using too small of
a bcolor_entry size, the last 32bytes of the bcolor_entry would be
overwritten.
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db944999a1bad94471966862cc38212019165937
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Sat Mar 9 22:53:27 2019 +0000
gitlab-ci: add panfrost to the gallium drivers build
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6ba67dd65c890237dd11ef43505d982431e5cc0
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Sat Mar 9 22:27:51 2019 +0000
panfrost: move #include to fix compilation
In standalone.h, the struct gl_context type is not declared by #includ'ing
mtypes.h:
In file included from src/gallium/drivers/panfrost/midgard/cmdline.c:24:
src/compiler/glsl/standalone.h:46:14: warning: ‘struct gl_context’ declared inside parameter list will not be visible outside of this definition or declaration
struct gl_context *ctx);
^~~~~~~~~~
This causes the following compilation failure:
src/gallium/drivers/panfrost/midgard/cmdline.c: In function ‘compile_shader’:
src/gallium/drivers/panfrost/midgard/cmdline.c:58:61: error: passing argument 4 of ‘standalone_compile_shader’ from incompatible pointer type [-Werror=incompatible-pointer-types]
prog = standalone_compile_shader(&options, 2, argv, &local_ctx);
^~~~~~~~~~
In file included from src/gallium/drivers/panfrost/midgard/cmdline.c:24:
src/compiler/glsl/standalone.h:43:28: note: expected ‘struct gl_context *’ but argument is of type ‘struct gl_context *’
struct gl_shader_program * standalone_compile_shader(
^~~~~~~~~~~~~~~~~~~~~~~~~
Fixes: e67e0726372ab65f4104 "panfrost: Implement Midgard shader toolchain"
Cc: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4d29c0455bf8540de3c006dd213ae1ccf2bc361
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Sat Mar 9 22:04:21 2019 +0000
panfrost: fix tgsi_to_nir() call
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109945
Fixes: 7da251fc721360fc28b9 "panfrost: Check in sources for command stream"
Cc: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5475434fa6f480016dea5df94553442a930ad57c
Author: Axel Davy <davyaxel0 at gmail.com>
Date: Sat Mar 9 14:29:07 2019 +0100
Revert "d3dadapter9: Support software renderer on any DRI device"
This reverts commit 0d0847659385e298badd6ef6ca4d0a9e537ae288.
It makes gitlab's travis fail. Revert until patch is fixed.
Signed-off-by: Axel Davy <davyaxel0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=597b5e27fa6d1662e01751aae7fde65896f7c8ef
Author: Axel Davy <davyaxel0 at gmail.com>
Date: Tue Feb 5 00:11:46 2019 +0100
st/nine: Change a few advertised caps
Most hw on the native platform advertise these
caps this way.
D3DCAPS_READ_SCANLINE: We don't really have hardware
support for that, but many games don't even check the
flag, and expect GetRasterStatus to work, which is
why we emulated it with a timer (like wine). So we
may as well advertise the cap.
D3DCURSORCAPS_LOWRES: I don't know what is the status
of this on X11, but I don't know of any dx9 game
running at height < 400 either.
D3DPTEXTURECAPS_TEXREPEATNOTSCALEDBYSIZE: The cap should
correspond to what the current generation of hw is doing.
Signed-off-by: Axel Davy <davyaxel0 at gmail.com>
Reviewed-by: Patrick Rudolph <siro at das-labor.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d3c37e2f9f03dfb7349e380c425a0956182488f
Author: Axel Davy <davyaxel0 at gmail.com>
Date: Mon Feb 4 23:42:06 2019 +0100
st/nine: Do not advertise CANMANAGERESOURCE
It doesn't seem the main vendors advertise it.
Signed-off-by: Axel Davy <davyaxel0 at gmail.com>
Reviewed-by: Patrick Rudolph <siro at das-labor.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8583e75d647dd2a726fdae359bae3785e17de67
Author: Axel Davy <davyaxel0 at gmail.com>
Date: Mon Feb 4 22:32:45 2019 +0100
st/nine: Do not advertise support for D15S1 and D24X4S4
The former is supported on Matrox cards but no other hw.
The latter isn't supported anywhere.
It is fine to not advertise them as supported,
and it could prevent apps to trigger weird rendering paths.
Signed-off-by: Axel Davy <davyaxel0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d0847659385e298badd6ef6ca4d0a9e537ae288
Author: Patrick Rudolph <siro at das-labor.org>
Date: Thu Feb 28 18:13:39 2019 +0100
d3dadapter9: Support software renderer on any DRI device
If D3D_ALWAYS_SOFTWARE is set for debugging purposes,
run on any DRI enabled platform.
Instead of probing for a compatible gallium driver (which might
fail if there's none) always use the KMS DRI software renderer.
Allows to run nine on i915 when D3D_ALWAYS_SOFTWARE=1.
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
Reviewed-by: Axel Davy <davyaxel0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7b9c09c7cd41dc91c5392e467b71216234e342e
Author: Axel Davy <davyaxel0 at gmail.com>
Date: Mon Feb 25 21:02:14 2019 +0100
st/nine: Disable depth write when nothing gets updated
I do not see any perf impact on radeonsi, but it
seems iris needs this.
It seems something sensible to do.
Signed-off-by: Axel Davy <davyaxel0 at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Andre Heider <a.heider at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7b31969767c0911b490022dc6bb67827e664644
Author: Elie Tournier <tournier.elie at gmail.com>
Date: Fri Feb 15 16:21:42 2019 +0000
virgl: Return an error if we use fp64 on top of GLES
Signed-off-by: Elie Tournier <elie.tournier at collabora.com>
Reviewed-by: <Gurchetan Singh gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f1514e1aa318b1d102ae59517b685b5606dc5e7
Author: Elie Tournier <tournier.elie at gmail.com>
Date: Fri Feb 15 16:18:25 2019 +0000
virgl: Set PIPE_CAP_DOUBLES when running on GLES This is a lie but no known app use fp64.
Signed-off-by: Elie Tournier <elie.tournier at collabora.com>
Reviewed-by: <Gurchetan Singh gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ad1e86bb075851fa53f6e218fc10bcbf68cc208
Author: Elie Tournier <tournier.elie at gmail.com>
Date: Fri Feb 15 16:14:10 2019 +0000
virgl: Add a caps to advertise GLES backend
Signed-off-by: Elie Tournier <elie.tournier at collabora.com>
Reviewed-by: <Gurchetan Singh gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da51e3f1b01b193360f87f29327bf3c0eded8f7a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Mar 9 01:39:20 2019 -0800
Revert MR 369 (Fix extract_i8 and extract_u8 for 64-bit integers)
This broke piles of image load store tests (179 failures on CI,
mesa_master build #15546, previous build right before this landed
was green). I'd rather not leave the tree on fire over the weekend,
so let's revert for now, and we can figure out what happened next week.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18e4bf65de2be6c20faa09985e7db55b1b8813bf
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 27 20:15:32 2019 -0800
nir/algebraic: Add missing 16-bit extract_[iu]8 patterns
No shader-db changes on any Intel platform.
v2: Use a loop to generate patterns. Suggested by Jason.
Reviewed-by: Matt Turner <mattst88 at gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55c1ac4b753d48fa2d97172216202264313e76b7
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 27 20:12:46 2019 -0800
nir/algebraic: Add missing 64-bit extract_[iu]8 patterns
No shader-db changes on any Intel platform.
v2: Use a loop to generate patterns. Suggested by Jason.
Reviewed-by: Matt Turner <mattst88 at gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9aaaac60808e54b1ecb5887d082a53e50c59f63a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 27 20:08:38 2019 -0800
nir/algebraic: Remove redundant extract_[iu]8 patterns
No shader-db changes on any Intel platform.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=37ee462e036b9b3bd90bc2b50fc4b05ac9a63560
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 27 19:52:12 2019 -0800
nir/algebraic: Fix up extract_[iu]8 after loop unrolling
Skylake, Broadwell, and Haswell had similar results. (Skylake shown)
total instructions in shared programs: 15256840 -> 15256837 (<.01%)
instructions in affected programs: 4713 -> 4710 (-0.06%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.06% max: 0.08% x̄: 0.06% x̃: 0.06%
total cycles in shared programs: 372286583 -> 372286583 (0.00%)
cycles in affected programs: 198516 -> 198516 (0.00%)
helped: 1
HURT: 1
helped stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10
helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
HURT stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10
HURT stats (rel) min: 0.01% max: 0.01% x̄: 0.01% x̃: 0.01%
No changes on any other Intel platform.
v2: Use a loop to generate patterns. Suggested by Jason.
Reviewed-by: Matt Turner <mattst88 at gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fdee457a4cb20f4587b5ec817aa1f9325bd5f1c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jan 10 13:39:05 2019 -0600
anv/pipeline: Move lower_explicit_io much later
Now that nir_opt_copy_prop_vars can properly handle array derefs on
vectors, it's safe to move UBO and SSBO lowering to late in the
pipeline. This should allow NIR to actually start optimizing SSBO
access.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=179d254cbaaa3f4ffcd5f9fef73cb413b7dc0e72
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jan 11 20:19:18 2019 -0600
intel/nir: Move lower_mem_access_bit_sizes to postprocess_nir
It doesn't really matter where this pass goes as long as it's after we
call nir_lower_explicit_io and before we go into the back-end. Putting
it brw_postprocess_nir lets us move nir_lower_explicit_io significantly
later in the pipeline.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad259482610048e0e3cc8fc0cacd4581f1256b5d
Author: Rob Clark <robdclark at gmail.com>
Date: Fri Mar 8 18:42:22 2019 -0500
freedreno/ir3: turn on [iu]mul_high
Which also requires uadd_carry lowering
Until recently this was lowered in glsl ir so it went unnoticed that we
weren't lowering it.
Fixes: 1d8994a63b5 glsl: [u/i]mulExtended optimization for GLSL
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53083e4fbc1d06c1ef241a7c8cae67d633a09a21
Author: Rob Clark <robdclark at gmail.com>
Date: Fri Mar 8 17:48:13 2019 -0500
freedreno/ir3: fix ir3_cmdline harder
Fixes: 45271702ec9 freedreno: fix ir3_cmdline build
Fixes: 7530d4abfcf glsl/freedreno/panfrost: pass gl_context to the standalone compiler
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fafead7b6257d0e3f0674a1f19563ed11d47ca8d
Author: Eric Anholt <eric at anholt.net>
Date: Wed Mar 6 11:08:43 2019 -0800
st/dri: Set the PIPE_BIND_SHARED flag on create_image_with_modifiers.
With createImage(), the caller was expected to set a SHARED flag if they
needed the ability to get a GEM handle. DRI3, wayland, and gbm all set
it, EGL_MESA_drm_image passes it through, and surfaceless doesn't need it
because there's no way to request a handle.
With the new createImageWithModifiers() DRI method to replace it, the
expectation is that you'll always be able to share the buffer, so the flag
is unnecessary in its arguments. However, we do need to tell gallium
about this expectation.
Without this, kmscube's modifiers path using
gbm_bo_create_with_modifiers(&modifier, 1) instead of
gbm_bo_create(SCANOUT | SHARED) will call the driver's resource_create()
function wtih PIPE_BIND_SHARED unset, so the driver (particularly
renderonly drivers) may allocate in such a way that it can't return an
answer from gbm_bo_get_handle(). I used to have a hack in v3d using
count==1 && modifier==LINEAR to indicate that you wanted SHARED anyway,
but that was dropped recently.
Fixes: 59527a36e975 ("v3d: Restructure RO allocations using
resource_from_handle.")
Reviewed-by: Kristian H. Kristensen <hoegsberg at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d1334d2a0f983e175ffe371bee33f4ce048f910
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 21 03:04:18 2018 -0800
iris: Use copy_region and staging resources to avoid transfer stalls
This is similar to intel_miptree_map_blit and intel_buffer_object.c's
temporary blits in i965.
Improves performance of DiRT Rally by 20-25% by eliminating stalls.
Breaks piglit's spec/arb_shader_image_load_store/host-mem-barrier,
by using the GPU to do uploads, exposing a st/mesa issue where it
doesn't give us memory_barrier() calls. This is a pre-existing issue
and will be fixed by a later patch (currently out for review).
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f67c8701799ec29083f40373f74027f9b1d6dbc6
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri Mar 8 20:56:38 2019 +0000
android: fix missing backspace for line continuation
Reported-by: Clayton Craft <clayton.a.craft at intel.com>
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109944
Fixes: e1d81decf7a093867f05 "build: make passing an incorrect pointer type a hard error"
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a8742d32799eeb52eb7dbd4fd134a028b099d4d
Author: Karol Herbst <kherbst at redhat.com>
Date: Tue Feb 26 11:58:11 2019 +0100
prog_to_nir: fix write from vps to FOG
for fragment programs we already treat fog as a single component value,
but for vp we didn't.
Fixes fog related piglit tests with my out of tree Nouveau nir patches.
Signed-off-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bca28deb46235cae3079dba29c5a62cf2168e4b3
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date: Wed Mar 6 17:05:23 2019 -0800
iris: Track last VS URB entry size
Return immediately if last VS URB entry size is good enough for BLORP
operation
v2: Fix comments (Caio)
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Suggested-by: Kenneth Graunke<kenneth at whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0a8fba69a300824ac83c8dad7985fe31885aef3
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date: Wed Mar 6 13:27:28 2019 -0800
iris: Refactor code to share 3DSTATE_URB_* packet
v2: 1) Set IRIS_DIRTY_URB bit (Caio)
2) Get rid of unnecessary function (Caio)
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Suggested-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e3d3f5b2c90ed79de85f69d4e0cc9b1b0760158
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Mar 5 11:09:13 2019 +0000
glx/meson: use full include path for dri_interface.h
Everything else uses `#include "GL/internal/dri_interface.h"` instead,
and this full path was even already used in other parts of GLX.
While at it, nothing uses `inc_gl_internal` anymore so let's remove it
as well.
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
Tested-by: Clayton Craft <clayton.a.craft at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1218d8cf71b35ab86ef0c25fdcf698e66dc14c0
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Mar 5 11:07:35 2019 +0000
hgl/meson: drop unused include directory
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
Tested-by: Clayton Craft <clayton.a.craft at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0de83bacf09c20b05b4ac67fdfb3e8e8f2e0108b
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 8 08:50:13 2019 -0700
intel/compiler: silence unitialized variable warning in opt_vector_float()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5ea56e411b3bab17ef0d4658f2c0bf23e8b91dc
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 8 08:49:44 2019 -0700
intel/decoders: silence uninitialized variable warnings in gen_print_batch()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5e2be3c737d6770b2973e2c9a84ebba9498487b
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 8 10:09:15 2019 -0700
st/mesa: init hash keys with memset(), not designated initializers
Since the compiler may not zero-out padding in the object.
Add a couple comments about this to prevent misunderstandings in
the future.
Fixes: 67d96816ff5 ("st/mesa: move, clean-up shader variant key decls/inits")
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2cff164cddb142238b6e37faefdbd3c9d2466ab
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri Mar 8 17:02:59 2019 +0000
gitlab-ci: fix llvm version (7 doesn't have a ".0")
Fixes: 85ee157283c667372baf "gitlab-ci: autotools needs to be told which llvm version to use"
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1d81decf7a093867f051786a5d7f6ce4d827ff1
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Nov 20 12:32:18 2018 +0000
build: make passing an incorrect pointer type a hard error
More or less any of this issue pointed out by the compiler is
a coding error. Make sure we flag it and bail loudly.
v2: - apply the change to autotools and scons as well (Emil)
- C++ doesn't need this, it's already an error and the flag
doesn't exist (Gert)
v3: - drop scons, flags are not checked so until someone adds that
functionality we can't have this.
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com> # v1
Reviewed-by: Emil Velikov <emil.velikov at collabora.com> # v1
[Emil: apply the same change to autotools and scons]
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=598f10eacca1488e580779fc9b6110ed9cba1f13
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Thu Mar 7 15:09:42 2019 +0000
r600: cast pointer to expected type
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-By: Gert Wollny <gert.wollny at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=85ee157283c667372baf7c03259cba08853f0067
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri Mar 8 16:02:11 2019 +0000
gitlab-ci: autotools needs to be told which llvm version to use
Fixes: 45d58cd91567b39f51af "gitlab-ci: only build the default (=latest) and oldest llvm versions"
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3006f9d8c06841745338582be72a89314dc8f973
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Mar 6 17:59:03 2019 +0000
gitlab-ci: only build the default (=latest) and oldest llvm versions
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08b70e1c2b82d8ddfa067baf686095b84ddbb636
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri Mar 8 15:33:39 2019 +0000
travis: clean up
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2f528bf21bc8c9afdbb37ee6b329a48f65c9a7a
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri Mar 8 15:05:15 2019 +0000
travis: drop unused vars
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=44c420aa1b9a40563011a2b1b656b14e6e87e910
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri Mar 8 15:04:54 2019 +0000
travis: fix meson build by letting `auto` do its job
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9cf85d3b78a0641f7b81bfbf828d2efeba590aa2
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Mar 5 11:49:33 2019 +0000
autotools: don't build libGLES*.so with GLVND
GLVND already provides these, so distro packagers have been deleting
them all along. Let's save ourselves the trouble and not build them in
the first place.
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b01524fff05eef66e8cd24f1c5aacefed4209f03
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Mar 5 11:46:38 2019 +0000
meson: don't build libGLES*.so with GLVND
GLVND already provides these, so distro packagers have been deleting
them all along. Let's save ourselves the trouble and not build them in
the first place.
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c387819f4b19a6da1255c63a7b2746feed2f9d9
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 8 08:07:23 2019 -0700
pipebuffer: s/PB_ALL_USAGE_FLAGS/PB_USAGE_ALL/
To fix build failure. I guess my meson configuration has assertions
disabled for some reason.
Trivial fix.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4381cf5939cd344af16197074e56555d8b5e738
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 7 16:14:32 2019 -0700
svga: remove SVGA_RELOC_READ flag in SVGA3D_BindGBSurface()
This fixes a rendering issue where UBO updates aren't always picked
up by drawing calls. This issue effected the Webots robotics
simulator. VMware bug 2175527.
Testing Done: Webots replay, piglit, misc Linux games
Reviewed-by: Thomas Hellstrom <thellstrom at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=07e8a31e494702e993a4fa1fa2a04ab3e3c4a011
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 6 10:16:57 2019 -0700
svga: refactor draw_vgpu10() function
The draw_vgpu10() function was huge. Move the code for preparing the
vertex buffers and the index buffer into separate functions.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53acd4c688909e62850d91120b798ff371d296ee
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 7 16:44:06 2019 -0700
st/mesa: whitespace, formatting fixes in st_cb_flush.c
Trivial.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67d96816ff50ad61e8f4ade9031c9cf221983ae6
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 6 10:23:59 2019 -0700
st/mesa: move, clean-up shader variant key decls/inits
Move the variant key declarations inside the scope they're used.
Use designated initializers instead of memset() calls.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76a10fc89e73a21771523a8c343c8f5727fbe16a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 5 14:20:29 2019 -0700
winsys/svga: use new pb_usage_flags enum type
And add a comment that we're implicitly converting PIPE_TRANSFER_
flags to PB_USAGE_ flags in one place. And statically assert that
the enum values match.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5f2b0d6b6ab462d5d8732a17493af2da400a9ef
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 5 19:47:25 2019 -0700
pipebuffer: whitespace fixes in pb_buffer.h
Reviewed-by: Neha Bhende <bhenden at vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b286e74df66e25cadd1c82d9ddc4d1fc3887b646
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 5 14:08:35 2019 -0700
pipebuffer: use new pb_usage_flags enum type
Use a new enum type instead of 'unsigned' to make things a bit more
understandable.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=daf567f79745dc0bdfa34966fed646cabd5bf563
Author: Charmaine Lee <charmainel at vmware.com>
Date: Tue Mar 5 19:36:48 2019 -0700
svga: add svga shader type in the shader variant
With this patch, the svga shader type will be saved in the shader variant,
and there is no need to pass in the shader type to the define/destroy
variant functions.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac6b33a50da7d0a46e9981dcc7f6b78bd94741e8
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 5 10:06:43 2019 -0700
gallium/util: add some const qualifiers in u_bitmask.c
And add/update comments.
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5a3a90c0cce016a0e130010c24eede4ed358046
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 5 10:05:18 2019 -0700
gallium/util: whitespace cleanups in u_bitmask.[ch]
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=686b7b1d48fea0ff62bdb177f9696316a02d2b07
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Thu Mar 7 16:57:10 2019 +0100
nir/linker: fix ARRAY_SIZE query with xfb varyings
For a non-array varying, it is expecting ARRAY_SIZE as 1, instead of 0.
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de31fb2f4f75b253e7d9e4617da6c1d04ae18df9
Author: Antia Puentes <apuentes at igalia.com>
Date: Sat Dec 22 18:40:29 2018 +0100
nir/linker: Fix TRANSFORM_FEEDBACK_BUFFER_INDEX
From the ARB_enhanced_layouts specification:
"For the property TRANSFORM_FEEDBACK_BUFFER_INDEX, a single integer
identifying the index of the active transform feedback buffer
associated with an active variable is written to <params>. For
variables corresponding to the special names "gl_NextBuffer",
"gl_SkipComponents1", "gl_SkipComponents2", "gl_SkipComponents3",
and "gl_SkipComponents4", -1 is written to <params>."
We were storing the xfb_buffer value, instead of the value
corresponding to GL_TRANSFORM_FEEDBACK_BUFFER_INDEX.
Note that the implementation assumes that varyings would be sorted by
offset and buffer.
Signed-off-by: Antia Puentes <apuentes at igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c0f411c27d57861be07add717b8e9bda86569e4
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Wed Nov 7 10:11:20 2018 +0100
nir/linker: use nir_gather_xfb_info
Instead of a custom ARB_gl_spirv xfb gather info pass.
In fact, this is not only about reusing code, but the current custom
code was not handling properly how many varyings are enumerated from
some complex types. So this change is also about fixing some corner
cases.
v2: Use util_bitcount, simplify current stage check (Kenneth)
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2a212ac2edfd326e6b4faa011bf08dc301a6a47
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Thu Jan 10 15:04:37 2019 +0100
nir/xfb: handle arrays and AoA of basic types
On OpenGL, a array of a simple type adds just one varying. So
gl_transform_feedback_varying_info struct defined at mtypes.h includes
the parameters Type (base_type) and Size (number of elements).
This commit checks this when the recursive add_var_xfb_outputs call
handles arrays, to ensure that just one is addded.
We also need to take into account AoA here
v2: use glsl_type_is_leaf from nir_types (Timothy Arceri)
v3: simplified aoa check, without the need ot using glsl_type_is_leaf,
using glsl_types_is_struct (Timothy Arceri)
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b65fecd8571f2f31633493b6c2d37bedef61c80
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Thu Mar 7 11:33:03 2019 +0100
nir_types: add glsl_type_is_struct helper
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d693746e99b79a78cc70c42b45e3fea3eaf9180
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Thu Mar 7 17:42:49 2019 +0100
nir/xfb: sort varyings too
Right now we are only re-sorting outputs. But it is better to sort too
varyings, as linker expect them to be sorted out (as it was done on
GLSL). For varyings, and to make easier to compute buffer_index, we
sort also by buffer. We could do the same for outputs, but we lack a
reason for that, so we left it as it is (just offset).
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf0b2ad486c954086b4aa6843fdfc20c4ed60e7d
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Wed Jan 9 18:19:45 2019 +0100
nir/xfb: adding varyings on nir_xfb_info and gather_info
In order to be used for OpenGL (right now for ARB_gl_spirv).
This commit adds two new structures:
* nir_xfb_varying_info: that identifies each individual varying. For
each one, we need to know the type, buffer and xfb_offset
* nir_xfb_buffer_info: as now for each buffer, in addition to the
stride, we need to know how many varyings are assigned to it.
For this patch, the only case where num_outputs != num_varyings is
with the case of doubles, that for dvec3/4 could require more than one
output. There are more cases though (like aoa), that will be handled
on following patches.
v2: updated after new nir general XFB support introduced for "anv: Add
support for VK_EXT_transform_feedback"
v3: compute num_varyings beforehand for allocating, instead of relying
on num_outputs as approximate value (Timothy Arceri)
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f68b9ac711b39d030e795820b61285d9524555a
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Wed Mar 6 15:15:54 2019 +0100
nir_types: add glsl_varying_count helper
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b62a8149abc9dd4ecef0b888d3a6bf04203231f4
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Nov 6 18:10:01 2018 +0100
nir/xfb: add component_offset at nir_xfb_info
Where component_offset here is the offset when accessing components of
a packed variable. Or in other words, location_frac on
nir.h. Different places of mesa use different names for it.
Technically nir_xfb_info consumer can get the same from the
component_mask, it seems somewhat forced to make it to compute it,
instead of providing it.
v2: rename local location_frac for comp_offset, more similar to the
intended use (Timothy Arceri)
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e72daf3e7023246fc960cb5e375ae81313f7803b
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Mar 8 14:51:02 2019 +0100
Revert "radv: execute external subpass barriers after ending subpasses"
This changes is actually wrong because we have to sync
before doing image layout transitions.
This fixes rendering issues in Batman, Path of Exile and
probably more titles.
This reverts commit 76c17cfd8da017ebd19be33ba6cef888957a6758.
Fixes: 76c17cfd8da ("radv: execute external subpass barriers after ending subpasses")
Cc: 19.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7271808df8b82bc1bbb9f222aeddc6604ee0354e
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Fri Nov 16 18:13:36 2018 +0000
intel/error2aub: support older style engine names
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a036eac029da21d28d0c90a05669d7c7694eb80b
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Sep 4 17:33:45 2018 +0100
intel/error2aub: deal with GuC log buffer
When Guc is enabled, the error state will contain a "global" buffer
for the GuC log buffer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c619ea945d6f3f0b2dfc87616f0183a78fd42049
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Aug 23 19:01:47 2018 +0100
intel/error2aub: add a verbose option
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca0161f890cd9b22cbb1c830e835b549e3010e7b
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Sep 4 14:45:37 2018 +0100
intel/error2aub: write GGTT buffers into the aub file
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b5dc2124fabaae3db42bab6639d507657e22866
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Sep 4 14:50:13 2018 +0100
intel/error2aub: store engine last ring buffer head/tail pointers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cdab19fa57ede4be26c7b8ab1a76652071ad63bd
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Sep 4 14:18:35 2018 +0100
intel/error2aub: annotate buffer with their address space
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=630a72827ab75161a143f09e65ecf2f12d10e0ed
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Sep 4 13:44:49 2018 +0100
intel/error2aub: parse other buffer types
We don't write them in the aub file yet.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0ea043888c1440c6f6f30d616ef5d2bf45bef46
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Sep 4 13:36:11 2018 +0100
intel/error2aub: strenghten batchbuffer identifier marker
Found out that some base64 data matched the '---' identifier. We can
avoid this by adding the surrounding spaces.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=650e6e5d339f96486104976efb8497105687f20d
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Sep 4 13:32:44 2018 +0100
intel/error2aub: identify buffers by engine
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a07f5262f0f80b842725c5cb69b9062a78c45da2
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Aug 23 18:06:22 2018 +0100
intel/error2aub: build a list of BOs before writing them
The error state contains several kind of BOs, including the context
image which we will want to write in a later commit. Because it can
come later in the error state than the user buffers and because we
need to write it first in the aub file, we have to first build a list
of BOs and then write them in the appropriate order.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=04ddff1aa46e22813b94cd452f959a8fc557603d
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Feb 22 23:31:56 2019 +0000
iris: Wire up EGL_IMG_context_priority
Add the missing PIPE_CAP_CONTEXT_PRIORITY_MASK and parsing of the context
construction flags.
Testcase: piglit/egl-context-priority
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2993088500365405516663fa48b1764e8c8d1ffa
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 24 00:27:09 2018 -0800
iris: Export a copy_region helper that doesn't flush
I'll want to use this for transfer maps, which already do their own
flushing. This lets us avoid a double flush, and also gives us more
control over the batch which is selected.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=335726fdaca2751a12c9cb515cdfd34b51e00049
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Mar 5 01:21:53 2019 -0800
iris: Spruce up "are we using this engine?" checks for flushing
We were using batch->contains_draw as a proxy for "are we even using
this engine?" That isn't quite right, because it only counts regular
draws. BLORP operations may have also rendered to a resource, which
needs to trigger flushing. To check for this, we also see if the
render and sometimes depth caches are non-empty.
We can also drop the "but there might already be stale data in the
cache even if we haven't emitted any commands yet" concern in the
comments. The kernel flushes caches between batches.
This may not be great but it's at least better than what was there.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0c214cceeada1e5d4afa89b1ce819c79d8b8c5b
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Thu Mar 7 08:19:02 2019 +0100
radeonsi/nir: Only set window_space_position for vertex shaders.
By mistake, this was previously set for all shaders.
It is a vertex shader property so only makes sense to
set it for vertex shaders.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-By: Timothy Arceri <tarceri at itsqueeze.com>
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1664de5924aa6d761be21afdee411654121515d1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Mar 7 11:45:13 2019 -0600
nir/builder: Add a build_deref_array_imm helper
Unlike most of the cases in which we do this by hand, the new helper
properly handles non-32-bit pointers.
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcf2a0122e9ccf3be8d1fa3bd18b8dedbebd6acf
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 5 16:06:31 2019 -0600
nir/builder: Cast array indices in build_deref_follower
There's no guarantee when build_deref_follower is called that the two
derefs have the same bit size destination. Insert a cast on the array
index in case we have differing bit sizes. While we're here, insert
some asserts in build_deref_array and build_deref_ptr_as_array. The
validator will catch violations here but they're easier to debug if we
catch them while building.
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd4c1458baba595aaff25ca1099c60a57d31772b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Mar 6 12:27:26 2019 -0600
nir/builder: Emit better code for iadd/imul_imm
Because we already know the immediate right-hand parameter, we can
potentially save the optimizer a bit of work.
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebbb6b8eaa06c0eac93fee689223c6a98d3f98bc
Author: Rob Clark <robdclark at gmail.com>
Date: Thu Mar 7 14:22:24 2019 -0500
freedreno/a6xx: perfcntrs
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40d8ed5ef356866eb6cb4592df789bd2a3b29061
Author: Rob Clark <robdclark at gmail.com>
Date: Wed Mar 6 10:34:53 2019 -0500
freedreno/a6xx: fix border-color swizzles
Fixes nearly all of the remaining
dEQP-GLES31.functional.texture.border_clamp.formats.* fails
Signed-off-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5d80ff2db36736636aede2040c716d7fb437286
Author: Rob Clark <robdclark at gmail.com>
Date: Wed Mar 6 10:04:21 2019 -0500
freedreno/a6xx: refactor fd6_tex_swiz()
We need a version of fd6_tex_swiz() that just returns the composed
swizzle without building part of the TEX_CONST_0 state. So just
refactor the existing function to build more of the TEX_CONST_0 state,
and leave fd6_tex_swiz() simply composing swizzles.
The small IBO state change (to use LINEAR for smaller sizes/levels) is
to match the state in fd6_tex_const_0(). It seems like maybe tiled
actually works at the smaller sizes but not if minification is in play,
so best just to make images match what we do for textures.
Signed-off-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8dc47490c8384ebab1be3d582e8e4ba93187f6fa
Author: Rob Clark <robdclark at gmail.com>
Date: Wed Mar 6 09:44:14 2019 -0500
freedreno/a6xx: remove astc_srgb workaround
Not used on a6xx, so remove some of the related plumbing that was copied
over from older gens.
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=45271702ec9b69f8e420940e4584e4b162188ccb
Author: Rob Clark <robdclark at gmail.com>
Date: Thu Mar 7 15:32:11 2019 -0500
freedreno: fix ir3_cmdline build
Fixes: 7530d4abfcf glsl/freedreno/panfrost: pass gl_context to the standalone compiler
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d53b1b621587bbdbc90f12eadf504888ab023b58
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 19 02:17:42 2018 -0800
iris: Drop PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
This cap is mainly for working around a r600 texture swizzle issue,
but it also controls whether ARB_texture_buffer_object (with legacy
formats) is enabled. I suspect the missing I/L/A/LA faking is why
I had it set in the first place.
Thanks to Ilia for pointing out that I shouldn't be setting this.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=809a81ec3a0b8666ec426a88b86fb133ae5f1bcb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 21 22:49:40 2019 -0800
iris: Properly support alpha and luminance-alpha formats
For texturing, we map alpha formats to the corresponding red format,
as many alpha formats are outright missing, and red is more efficient
when sampling anyway.
When rendering to A8_UNORM, we use that format directly, so the image
gets the shader output's .a/.w channel, rather than the .r/.x channel.
All other A* formats are non-renderable, so we can't do much and just
mark them as unsupported for rendering. Fortunately, GL only requires
rendering to A8_UNORM, so that works out.
According to Andre Heider and Timur Kristóf, this fixes font rendering
in Witcher 1 (via nine). Andre also reported that it fixes Unigine
Heaven (presumably via nine).
v2: Use the same swizzle for both sampler views and "render targets".
BLORP expects the read swizzle, and will take the inverse when
setting up the destination swizzle (and actually applying it in
the shaders). We ignore the format swizzle when setting up normal
rendering SURFACE_STATEs, which is necessary because it would be
an illegal shader channel select combination. Thanks to Jason
Ekstrand for pointing out that BLORP took an inverse swizzle.
Tested-by: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbc51c4c956bb681c52e3163f73051303b24d8b8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 15:34:30 2018 -0800
iris: Defer uploading sampler state tables until draw time
Gallium might call us multiple times to bind subsets of the samplers,
at which point we'd recreate the table a bunch of times. It doesn't
really buy us anything to do it here - even if we defer to draw time,
the dirty tracking ensures we'll only do it on the first draw after a
bind_sampler_states() call.
We now use the number of samplers specified by the shader instead of
the binding count. If this number changes, we flag sampler state as
dirty so we re-upload a table with the right number of entries.
This also fixes a bug where ice->state.need_border_colors was never
unset, so once something needed border colors, the pool would always
be pinned in all future batches.
v2: Explicitly flag sampler states as dirty, rather than assuming that
bind_sampler_states() will be called if the program texture count
changes. While this may be true for st/mesa, it isn't the case for
Gallium HUD.
Tested-by: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9caabd6c5f15e8c0e7ebe0147372d16750e2a20b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 28 01:13:33 2019 -0800
iris: Plumb through ISL_SWIZZLE_IDENTITY in buffer surface emitters
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4787bc944a2d219dd04201eef699d9f999b479b8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 28 01:13:33 2019 -0800
isl: Add a swizzle parameter to isl_buffer_fill_state()
This is necessary for legacy texture buffer object formats, where we'll
need to use a swizzle to fake e.g. luminance.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=575f8e8b60ab06e559a62ffe90913453352f32b4
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Mar 7 16:59:53 2019 +0000
iris: fix decode_get_bo callback
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: acb50d6b1ff1b7 ("intel/decoders: handle decoding MI_BBS from ring")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55e4759c8da5eec71ca2f5ad2460a9ae7137ac39
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 14:43:15 2019 +0100
virgl: remove unused variable
This variable is now unused, so let's remove it.
Fixes: 9c4930946a5 (virgl: add encoder functions for new protocol)
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=44620d4ef7d9ac10de489a8238b7f80dce2da510
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 14:41:54 2019 +0100
virgl: remove unused variable
This variable is now unused, so let's remove it.
Fixes: db77573d7ba (virgl: modify how we handle GL_MAP_FLUSH_EXPLICIT_BIT)
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=524934586b8cdc2e745dcf5ea83aeec50c1eefbe
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 14:40:04 2019 +0100
virgl: remove unused variable
This variable is now unused, so let's remove it.
Fixes: c19aedcf1a8 (virgl: don't mark unclean after a flush)
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=af29c93f229a09588a5abd2185e79a1deb1468ea
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Wed Mar 6 14:36:15 2019 +0100
virgl: remove unused variables
These variables are now unused, let's remove them to get rif of a few
warnings.
Fixes: f0e71b10888 (virgl: use transfer queue)
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e269c0ac2d98dd3a30a7af32a5a1895a0df96b5
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Mar 7 16:14:13 2019 +0000
iris: fix decoder call
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: acb50d6b1ff1b7 ("intel/decoders: handle decoding MI_BBS from ring")
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b3871bc7f4dc89895551ab87ee7b25b166e1a6d
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Sep 3 15:11:08 2018 +0100
intel/aub_write: factorize context image/pphwsp/ring creation
We allocate GGTT entries and physical addresses are we create engines
rather than having a fixed layout.
Context images now receive a parameter argument which is used to setup
pml4 & ring buffer addresses.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1a2c72e76fa5ace071d6ff91654918f562c292c
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Sep 3 15:10:06 2018 +0100
intel/aub_write: turn context images arrays into functions
We'll make them more parameterized in a later commit.
As this is just a transitional commit, we allow ourself to leak the
context images allocated in get_context_init(). We'll fix this in the
next commit.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e14c9b7dbb1c1ee730573cc712cde29659e94c5
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Fri Aug 24 00:03:28 2018 +0100
intel/aub_write: store the physical page allocator in struct
We want to use this allocator in the next commit for GGTT pages.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0343a3b42b67a6255c9e8cd132b0cef2d88e429b
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Sat Aug 25 01:40:29 2018 +0100
intel/aub_write: log mmio writes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ef46972d953a3821ea083f36f930407f0663af8
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Sun Aug 26 14:35:30 2018 +0100
intel/aub_write: switch to use i915_drm engine classes
Prepare aub write to deal with multiple engine instances. We don't
pass the instance number yet this could be done in the future by
having a 2 dimensional array of struct engine.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Acked-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a81f5c255a3737f4855496fcd4ff229993f861f
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Fri Aug 24 00:37:03 2018 +0100
intel/aub_write: break execlist write in 2
We want to reuse the execlist submission, but won't need the ring
buffer update.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69ee5bde4e3ce8c88e16bb16e0bccf440cf516ac
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Aug 27 00:19:29 2018 +0100
intel/aub_write: write header in init
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01443f34b4133e23b04718a0a26f317d658de760
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Aug 23 20:36:16 2018 +0100
intel/aub_write: split comment section from HW setup
In the future we'll want error2aub to reuse the context image saved by
i915 instead of the default one we write in intel_dump_gpu.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b42adff1421babe402e8c9269c435ea49608006
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Aug 23 17:07:08 2018 +0100
intel/aub_read: reuse defines from gen_context
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf93084f44965d1daae688fae46615d310e41385
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Sep 4 15:45:32 2018 +0100
intel/decoders: limit number of decoded batchbuffers
IGT has a test to hang the GPU that works by having a batch buffer
jump back into itself, trigger an infinite loop on the command stream.
As our implementation of the decoding is "perfectly" mimicking the
hardware, our decoder also "hangs". This change limits the number of
batch buffer we'll decode before we bail to 100.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=acb50d6b1ff1b73a66e88862c99b65d87869e01d
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Aug 28 11:41:42 2018 +0100
intel/decoders: handle decoding MI_BBS from ring
An MI_BATCH_BUFFER_START in the ring buffer acts as a second level
batchbuffer (aka jump back to ring buffer when running into a
MI_BATCH_BUFFER_END).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec526d6ba0bdb996416b7479330a424ff737df81
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Sun Aug 26 13:52:47 2018 +0100
intel/decoders: add address space indicator to get BOs
Some commands like MI_BATCH_BUFFER_START have this indicator.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e8d5b5ed48aaa37d8b83c2203f45ce55d557351
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Thu Mar 7 13:45:14 2019 +0000
vulkan/overlay: fix missing var rename in previous commit
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d141472d0ec1db2391a54919bc480eaa1eac36b6
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Mar 5 15:57:34 2019 +0000
vulkan/util: use the platform defines in vk.xml instead of hard-coding them
See also: 3d4238d26c5de4a0f7a5 "anv: use the platform defines in vk.xml
instead of hard-coding them"
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4324dcefb749983e45d2ae7b005e1a6de4a3064
Author: Andre Heider <a.heider at gmail.com>
Date: Sun Feb 10 18:31:59 2019 +0100
iris: add support for tgsi_to_nir
The Gallium Nine state tracker now works on iris.
Also tested with GALLIUM_HUD and Star Wars: Knights of the Old
Republic on WINE (GL_ATI_fragment_shader).
Signed-off-by: Andre Heider <a.heider at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b010f35578205eecbe574e8ef3914b398ba0b55
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Mar 6 12:30:22 2019 +0200
nir: free dead_ctx in case of no progress
Fixes a leak:
==7576== 320 (48 direct, 272 indirect) bytes in 1 blocks are definitely lost in loss record 26 of 26
==7576== at 0x4C2EE3B: malloc (vg_replace_malloc.c:309)
==7576== by 0x53EF0E4: ralloc_size (ralloc.c:119)
==7576== by 0x53EF0C2: ralloc_context (ralloc.c:113)
==7576== by 0x5471F64: nir_split_per_member_structs (nir_split_per_member_structs.c:176)
==7576== by 0x51288CF: anv_shader_compile_to_nir (anv_pipeline.c:216)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4900c0cff4cc1a5966d70402a8ee01b7495d3a0e
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Mar 6 12:27:30 2019 +0200
anv: call blob_finish when done with it
Fixes leaks from anv_device_upload_nir:
==7345== 8,192 bytes in 2 blocks are definitely lost in loss record 24 of 24
==7345== at 0x4C2ED78: malloc (vg_replace_malloc.c:308)
==7345== by 0x4C31393: realloc (vg_replace_malloc.c:836)
==7345== by 0x54E0848: grow_to_fit (blob.c:67)
==7345== by 0x54E0BE5: blob_reserve_bytes (blob.c:166)
==7345== by 0x54E0C7C: blob_reserve_intptr (blob.c:186)
==7345== by 0x54704A7: nir_serialize (nir_serialize.c:1091)
==7345== by 0x512F97D: anv_device_upload_nir (anv_pipeline_cache.c:756)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9555f37d5b15c86aed73d0dab8d514751e12a54
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Mar 6 10:49:21 2019 +0200
anv: use anv_gem_munmap in block pool cleanup
Use anv_gem_munmap for unmap when softpin in use, this corresponds to
anv_gem_mmap used in anv_block_pool_expand_range. This fixes valgrind
errors seen for each pool when softpin is in use:
==25581== 262,144 bytes in 1 blocks are definitely lost in loss record 31 of 31
==25581== at 0x50E77E8: anv_gem_mmap (anv_gem.c:96)
==25581== by 0x50EEE2B: anv_block_pool_expand_range (anv_allocator.c:543)
==25581== by 0x50EEB51: anv_block_pool_init (anv_allocator.c:477)
==25581== by 0x50EF7EF: anv_state_pool_init (anv_allocator.c:920)
==25581== by 0x510B8EB: anv_CreateDevice (anv_device.c:2031)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=744b8e1c12f2f3857070a895bf6a4351f071a3f9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 6 14:49:39 2019 -0800
iris: Fix MOCS for blits and clears
I915_MOCS_CACHED is the wrong value. Expose mocs() and use that.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecceb076e5c99cea94b853a9600947fe78b3ca74
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Wed Apr 4 16:01:21 2018 +1000
st/glsl: start spilling out common st glsl conversion code
The NIR and TGSI paths are currently intertwined which makes it
not only hard to follow but also makes it hard to take advantage
of the differences in IR.
Here we take the first step to splitting that path apart. With
this we take the opportunity to no longer call the GLSL IR
optimisation passes after the final lowering calls for NIR. We
can instead just use the NIR passes which can produce better code
and should also result in faster compile times.
The speed-up can be measured in some dolphin uber shaders due to
no longer calling lower_if_to_cond_assign() for example
dolphin/ubershaders/120.shader_test goes from ~1.63 -> ~1.53
seconds on my machine.
There are some code changes as a result of not calling
lower_if_to_cond_assign(), this is because it flattens ifs that
contain UBOs where as NIR's peephole select doesn't. This is
were most of the regressions in Max Waves happens with shader-db.
shader-db results (VEGA):
Totals from affected shaders:
SGPRS: 2349056 -> 2349640 (0.02 %)
VGPRS: 1322160 -> 1323300 (0.09 %)
Spilled SGPRs: 21190 -> 21527 (1.59 %)
Spilled VGPRs: 99 -> 99 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 72 -> 72 (0.00 %) dwords per thread
Code Size: 57260904 -> 57270932 (0.02 %) bytes
Compile Time: 1107186 -> 1022942 (-7.61 %) milliseconds
LDS: 786 -> 786 (0.00 %) blocks
Max Waves: 391932 -> 391619 (-0.08 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2fd96a563bbb63d8e3c1f874c65c1350fb19a0d
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Feb 21 12:15:18 2019 +1100
radeonsi/nir: stop calling nir_lower_returns()
We now call this for all drivers in glsl_to_nir() instead.
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=673f4f69a87708f490741bb6deeb217b1b2d25e1
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Feb 21 11:54:09 2019 +1100
i965: stop calling nir_lower_returns()
We now call this for all drivers in glsl_to_nir() instead.
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e60d5a501f311fa5e7bca5335adc6013dc1aeb9
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Wed Feb 20 17:13:49 2019 +1100
glsl: use NIR function inlining for drivers that use glsl_to_nir()
glsl_to_nir() is still missing support for converting certain
functions to NIR, so for those we use the GLSL IR optimisations
to remove the functions.
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7530d4abfcf9d39fb1b4abeb77cdbf6cf1d411a7
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Fri Feb 22 11:51:24 2019 +1100
glsl/freedreno/panfrost: pass gl_context to the standalone compiler
This allows us to use the ctx with glsl_to_nir() in a following
patch.
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15b83b3af972fe32de4b1730ef6aff110e5da49a
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Mar 5 12:19:10 2019 +0000
vulkan/overlay: drop dependency on validation layer headers
v2: reimplement layer chain info getters (Eric)
v3: make it compile.. (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=530927d3f6a303d9ef1eb1e839566ccb0e813036
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Mar 5 10:38:14 2019 +0000
vulkan/util: generate instance/device dispatch tables
This will be used by the overlay instead of system installed
validation layers helpers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Acked-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee491a4987d0b1698971343dce9f5460b1521e9a
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Feb 25 23:01:02 2019 +0000
vulkan/util: make header available from c++
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffa9082c406d17680c0ceeeac921ace5e793e5af
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Wed Feb 27 20:44:27 2019 +0100
iris: setup EdgeFlag Vertex Element when needed.
If Vertex Shader uses EdgeFlag the hardware request that it is setup
as the last VERTEX_ELEMENT_STATE. If SGVS are add at draw time we
need to also reconfigure the last 3DSTATE_VF_INSTANCING so its
VertexElementIndex points to the new Vertex Element that contains
the EdgeFlag.
So if draw parameters or edgeflag are not used the CSO generated at
iris_create_vertex_element is sent directly in the batches. But if
edge flag is used we adjust last VERTEX_ELEMENT_STATE and
last 3DSTATE_VF_INSTANCING using their alternative edge flag version
we generate at iris_create_vertex_element and store at the CSO.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4d2da1f1471a742de7156e45ca52f83c75f0ba9
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 21 12:47:37 2019 -0800
v3d: Include a count of register pressure in the RA failure dumps.
You usually want to go find the highest pressure and figure out why you
couldn't spill or what pattern led to a bunch of pressure leading to that
point.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=71ffa00fc66110a4062dc935d3548ebd0eb12f9e
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Mar 6 22:35:31 2019 +0100
radv: enable lower_mul_2x32_64
Fixes: 58bcebd987b ("spirv: Allow [i/u]mulExtended to use new nir opcode")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ab1b1d0227499b7ff6a61fdebe75693212a67f5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 4 17:02:39 2019 -0600
st/nir: Move 64-bit lowering later
Now that we have a loop unrolling cost function and loop unrolling isn't
going to kill us the moment we have a 64-bit op in a loop, we can go
ahead and move 64-bit lowering later. This gives us the opportunity to
do more optimizations and actually let the full optimizer run even on
64-bit ops rather than hoping one round of opt_algebraic will fix
everything. This substantially reduces both fp64 shader compile times
and the resulting code size.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=656ace3dd85b2eb8c565383763a00d059519df4c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 4 16:11:57 2019 -0600
intel/nir: Move 64-bit lowering later
Now that we have a loop unrolling cost function and loop unrolling isn't
going to kill us the moment we have a 64-bit op in a loop, we can go
ahead and move 64-bit lowering later. This gives us the opportunity to
do more optimizations and actually let the full optimizer run even on
64-bit ops rather than hoping one round of opt_algebraic will fix
everything. This substantially reduces both fp64 shader compile times
and the resulting code size. On the vs-isnan-dvec test from piglit:
Before this commit:
1684.63s user 17.29s system 99% cpu 28:28.24 total
101479 instructions. 0 loops. 802452 cycles. 79:369 spills:fills.
Peak memory usage (according to massif): 1.435 GB
After this commit:
179.64s user 7.75s system 99% cpu 3:07.92 total
57316 instructions. 0 loops. 459287 cycles. 0:0 spills:fills.
Peak memory usage (according to massif): 531.0 MB
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e02959f442ed6546fb632a153ffc32848968038f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 4 15:55:19 2019 -0600
nir/lower_doubles: Inline functions directly in lower_doubles
Instead of trusting the caller to already have created a softfp64
function shader and added all its functions to our shader, we simply
take the softfp64 shader as an argument and do the function inlining
ouselves. This means that there's no more nasty functions lying around
that the caller needs to worry about cleaning up.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f25ca337b40f1d5846ac146f00fba77b1610be37
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 4 16:17:02 2019 -0600
nir/deref: Expose nir_opt_deref_impl
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de8d80f9cc210367246382c0f1cb30c64fd7da4f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 4 15:32:36 2019 -0600
nir/inline_functions: Break inlining into a builder helper
This pulls the guts of function inlining into a builder helper so that
it can be used elsewhere. The rest of the infrastructure is still
needed for most inlining cases to ensure that everything gets inlined
and only ever once. However, there are use-cases where you just want to
inline one little thing. This new helper also has a neat trick where it
can seamlessly inline a function from one nir_shader into another.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a6b1d058076923fb98d44ac1d2b1bc314635800
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 4 14:39:40 2019 -0600
glsl/nir: Inline functions in float64_funcs_to_nir
This doesn't really change anything as the functions will all get
inlined anyway. However it does let us do a bit of the work earlier and
in a common place.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=82d9a37a59c94ba3678b33acb9f2749cbbd7bfcc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sun Mar 3 10:00:14 2019 -0600
glsl/nir: Add a shared helper for building float64 shaders
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8993e0973f7d0cfb211e0c39de82ef2497584df3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 4 16:01:23 2019 -0600
intel/nir: Drop an unneeded lower_constant_initializers call
Even though this is technically a step in the function inlining process
as laid out in nir_inline_functions.c, it's not really needed. We
already have constant initializers lowered here and no new ones are
added by appending the softfp64 functions.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa4824c1db949bfd5a4f21436c81089892c6110c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sun Mar 3 10:10:46 2019 -0600
intel/debug: Add a debug flag to force software fp64
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ce1aea88b9a8bd037fbddfc0399ebc483349174
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 4 22:54:44 2019 -0600
i965: Compile the fp64 program based on nir options
Instead of looking the devinfo directly, look at the lowering options we
provided to NIR. This is more accurate as it's now checking for "do we
need full software lowering" rather than a hardware bit.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9314084237d50e109ab575fca8696da28cf76798
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sun Mar 3 09:24:12 2019 -0600
nir: Teach loop unrolling about 64-bit instruction lowering
The lowering we do for 64-bit instructions can cause a single NIR ALU
instruction to blow up into hundreds or thousands of instructions
potentially with control flow. If loop unrolling isn't aware of this,
it can unroll a loop 20 times which contains a nir_op_fsqrt which we
then lower to a full software implementation based on integer math.
Those 20 invocations suddenly get a lot more expensive than NIR loop
unrolling currently expects. By giving it an approximate estimate
function, we can prevent loop unrolling from going to town when it
shouldn't.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebb3695376499c276d4e1508836ce6b38faf1390
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Mar 1 17:39:54 2019 -0600
nir: Expose double and int64 op_to_options_mask helpers
We already have one internally for int64 but we don't have a similar one
for doubles so we'll have to make one.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca2b5e9069177ea603efbe250e675dc7d194ef90
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Feb 12 12:55:28 2019 +0100
compiler/nir: add an is_conversion field to nir_op_info
This is set to True only for numeric conversion opcodes.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55e6454d5e9dae6f8f29992af83f99217446da38
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 27 15:53:55 2019 -0800
intel/fs: Fix extract_u8 of an odd byte from a 64-bit integer
In the old code, we would generate the exact same instruction for
extract_u8(some_u64, 0) and extract_u8(some_u64, 1). The mask-a-word
trick only works for even numbered bytes.
This fixes the (new) piglit test
tests/spec/arb_gpu_shader_int64/execution/fs-ushr-and-mask.shader_test.
v2: Use a SHR instead of an AND. This saves an instruction compared to
using two moves. Suggested by Jason.
Fixes: 6ac2d169019 ("i965/fs: Fix extract_i8/u8 to a 64-bit destination")
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4aaf139ea4cc7c4703e1906e0074f87f76c8e4cc
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 27 15:52:18 2019 -0800
intel/fs: nir_op_extract_i8 extracts a byte, not a word
Fixes: 6ac2d169019 ("i965/fs: Fix extract_i8/u8 to a 64-bit destination")
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbf20a1ca366094509ddfb1eedc943524a92c29f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 26 11:24:56 2019 -0800
intel/compiler: Silence unused parameter warning in brw_interpolation_map.c
The parameter is never used, and it's not part of a common interface
idiom. Remove it.
src/intel/compiler/brw_interpolation_map.c: In function ‘brw_setup_vue_interpolation’:
src/intel/compiler/brw_interpolation_map.c:62:59: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
const struct gen_device_info *devinfo)
^~~~~~~
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dea19138dd691c69ad4150e97b6f40ec4f0c7550
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 26 11:18:49 2019 -0800
intel/compiler: Silence many unused parameter warnings in brw_eu.h
In file included from src/intel/compiler/brw_eu_util.c:34:0:
src/intel/compiler/brw_eu.h: In function ‘brw_message_desc_header_present’:
src/intel/compiler/brw_eu.h:288:63: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
brw_message_desc_header_present(const struct gen_device_info *devinfo,
^~~~~~~
src/intel/compiler/brw_eu.h: In function ‘brw_message_ex_desc’:
src/intel/compiler/brw_eu.h:296:51: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
brw_message_ex_desc(const struct gen_device_info *devinfo,
^~~~~~~
src/intel/compiler/brw_eu.h: In function ‘brw_message_ex_desc_ex_mlen’:
src/intel/compiler/brw_eu.h:303:59: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
brw_message_ex_desc_ex_mlen(const struct gen_device_info *devinfo,
^~~~~~~
src/intel/compiler/brw_eu.h: In function ‘brw_sampler_desc_binding_table_index’:
src/intel/compiler/brw_eu.h:337:68: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
brw_sampler_desc_binding_table_index(const struct gen_device_info *devinfo,
^~~~~~~
src/intel/compiler/brw_eu.h: In function ‘brw_sampler_desc_sampler’:
src/intel/compiler/brw_eu.h:344:56: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
brw_sampler_desc_sampler(const struct gen_device_info *devinfo, uint32_t desc)
^~~~~~~
src/intel/compiler/brw_eu.h: In function ‘brw_sampler_desc_return_format’:
src/intel/compiler/brw_eu.h:371:62: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
brw_sampler_desc_return_format(const struct gen_device_info *devinfo,
^~~~~~~
src/intel/compiler/brw_eu.h: In function ‘brw_dp_desc_binding_table_index’:
src/intel/compiler/brw_eu.h:405:63: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
brw_dp_desc_binding_table_index(const struct gen_device_info *devinfo,
^~~~~~~
src/intel/compiler/brw_eu.h: In function ‘brw_dp_a64_untyped_atomic_desc’:
src/intel/compiler/brw_eu.h:754:41: warning: unused parameter ‘exec_size’ [-Wunused-parameter]
unsigned exec_size, /**< 0 for SIMD4x2 */
^~~~~~~~~
src/intel/compiler/brw_eu.h: In function ‘brw_dp_a64_untyped_atomic_float_desc’:
src/intel/compiler/brw_eu.h:775:47: warning: unused parameter ‘exec_size’ [-Wunused-parameter]
unsigned exec_size,
^~~~~~~~~
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=89241eeafc59e821c76d4f837f1078247dd77331
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Nov 20 13:36:17 2018 +0000
meson: remove unused include_directories(vulkan)
The correct include path is "vulkan/…".
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad862c36e5e175d9bf2d112927be7348fb3560f7
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Mar 5 12:32:13 2019 +0000
meson: fix with_dri2 definition for GNU Hurd
Suggested-by: Dylan Baker <dylan at pnwbakers.com>
Cc: Timo Aaltonen <tjaalton at debian.org>
Cc: James Clarke <jrtc27 at debian.org>
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b49726afd43739979a08de6e410e78ead5a26337
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Wed Mar 6 11:43:56 2019 +0000
radv: set num_components on vulkan_resource_index intrinsic
In 61e009d2c4e4df we changed the number of components in the
vulkan_resource_index intrinsic and forgot the update Radv's code for
it.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 61e009d2c4e4df ("spirv: Use the same types for resource indices as pointers")
Reviewed-by: Samuel Pitoiset samuel.pitoiset at gmail.com
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54522d05065d6ff1b37005c91e503b4d4f11ed67
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Tue Mar 5 16:07:12 2019 +1100
nir: rename glsl_type_is_struct() -> glsl_type_is_struct_or_ifc()
Replace done using:
find ./src -type f -exec sed -i -- \
's/glsl_type_is_struct(/glsl_type_is_struct_or_ifc(/g' {} \;
Acked-by: Karol Herbst <kherbst at redhat.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e16a27fcf867c8be5ba94470d78f76348f1e8c07
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Tue Mar 5 15:58:49 2019 +1100
glsl: rename record_types -> struct_types
Acked-by: Karol Herbst <kherbst at redhat.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8294295dbdc053c92065844f2079aef8da05db9b
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Tue Mar 5 15:55:57 2019 +1100
glsl: rename record_location_offset() -> struct_location_offset()
Replace done using:
find ./src -type f -exec sed -i -- \
's/record_location_offset(/struct_location_offset(/g' {} \;
Acked-by: Karol Herbst <kherbst at redhat.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=88d8c4e29003bddeb3836a0af2a2d4dddf3ba9ac
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Tue Mar 5 15:46:14 2019 +1100
glsl: rename get_record_instance() -> get_struct_instance()
Replace done using:
find ./src -type f -exec sed -i -- \
's/get_record_instance(/get_struct_instance(/g' {} \;
Acked-by: Karol Herbst <kherbst at redhat.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=81ee2cd8ba5a0145520e849e20c1a8e43f78c6fa
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Tue Mar 5 15:05:52 2019 +1100
glsl: rename is_record() -> is_struct()
Replace was done using:
find ./src -type f -exec sed -i -- \
's/is_record(/is_struct(/g' {} \;
Acked-by: Karol Herbst <kherbst at redhat.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=272e927d0e9fed6e791d706ff5d895b6c2036fc0
Author: Karol Herbst <kherbst at redhat.com>
Date: Thu Jul 12 15:02:27 2018 +0200
nir/spirv: initial handling of OpenCL.std extension opcodes
Not complete, mostly just adding things as I encounter them in CTS. But
not getting far enough yet to hit most of the OpenCL.std instructions.
Anyway, this is better than nothing and covers the most common builtins.
v2: add hadd proof from Jason
move some of the lowering into opt_algebraic and create new nir opcodes
simplify nextafter lowering
fix normalize lowering for inf
rework upsample to use nir_pack_bits
add missing files to build systems
v3: split lines of iadd/sub_sat expressions
Signed-off-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0b47ec4df0eafe4f4afddc2a0594b392c27f426
Author: Karol Herbst <kherbst at redhat.com>
Date: Mon Jan 14 18:36:37 2019 +0100
nir/vtn: add support for SpvBuiltInGlobalLinearId
v2: use formula with fewer operations
Signed-off-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f48c6729650e0a81b1a12487188163ba351571c8
Author: Karol Herbst <kherbst at redhat.com>
Date: Thu Jul 19 16:39:58 2018 +0200
nir: add support for address bit sized system values
v2: add assert in else clause
make local group intrinsics 32 bit wide
v3: always use 32 bit constant for local_size
v4: add comment by Jason
Signed-off-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f8257fb0b022448eaee7c7d843fcf7309776d83
Author: Karol Herbst <kherbst at redhat.com>
Date: Thu Jul 19 13:04:14 2018 +0200
nir/spirv: improve parsing of the memory model
v2: add some vtn_fail_ifs
Signed-off-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d48359a2c5670d55f24e91229f59efc6368dcba
Author: Karol Herbst <kherbst at redhat.com>
Date: Mon Mar 4 19:11:12 2019 +0100
nir: replace magic numbers with M_PI
we define it inside 'include/c99_math.h' so it is safe to use.
Signed-off-by: Karol Herbst <kherbst at redhat.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69cc6272fbc1991d83b9e739acf5d464e8e905c6
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Fri Mar 1 13:15:31 2019 -0800
anv: Implement VK_EXT_external_memory_host
v2: Ignore the import if handleType == 0. (Jason)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c655c47db76fd972beed11b8e3c4f5c590d1d44
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 21:37:47 2019 -0800
v3d: Drop the V3D 3.x vpm read dead code elimination.
We now have NIR dead code eliminating our VPM reads, so this shouldn't be
necessary.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8ee1f8eaf5ea7d688621eac8cd8b2729626d89f
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 21:34:22 2019 -0800
v3d: Eliminate the TLB and TLBU files.
We can just use the magic register file like we do for other magic waddrs.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=110f14d4b4bdee779a35c26e3224a9d28eb81fa7
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 10:17:59 2019 -0800
v3d: Use ldunif instructions for uniforms.
The idea is that for repeated use of the same uniform, we could avoid
loading it on each consumer. The results look pretty good.
total instructions in shared programs: 6413571 -> 6521464 (1.68%)
total threads in shared programs: 154214 -> 154000 (-0.14%)
total uniforms in shared programs: 2393604 -> 2119629 (-11.45%)
total spills in shared programs: 4960 -> 4984 (0.48%)
total fills in shared programs: 6350 -> 6418 (1.07%)
Once we do scheduling at the NIR level, the register pressure (and thus
also instructions) issues we see here will drop back down.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4036fce8fd75277567894afc595e16a4742d4587
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 09:19:40 2019 -0800
v3d: Add support for register-allocating a ldunif to a QFILE_TEMP.
On V3D 4.x, we can use ldunifrf to load uniforms to any register, and this
will let us schedule the ldunif wherever we want in the program.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=70df3882197853ab50fd41984ae2a6f9a412223a
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 09:13:43 2019 -0800
v3d: Drop the old class bits splitting up the accumulators.
This seems to be left over from vc4, and I don't use them any more.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dff1fc04e0be93ff45744d2d75d8b643cf59ecfc
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 09:05:05 2019 -0800
v3d: Add support for vir-to-qpu of ldunif instructions to a temp.
We can load a uniform to any register, so add support for non-ALU
instructions with sig.ldunif to a temp.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4739181a160cd941f7af78074c4f4ac7c6a1fd76
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 18:36:05 2019 -0800
v3d: Switch implicit uniforms over to being any qinst->uniform != ~0.
I'm not sure why I didn't do this before -- it's clearly much simpler to
add dumping of the extra thing than to have it as another implicit source.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e98f02d887dada530595bc0c74292d4678c5e1a
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 10:49:25 2019 -0800
v3d: Do uniform rematerialization spilling before dropping threadcount
This feels like the right tradeoff for threads vs uniforms, particularly
given that we often have very short thread segments right now:
total instructions in shared programs: 6411504 -> 6413571 (0.03%)
total threads in shared programs: 153946 -> 154214 (0.17%)
total uniforms in shared programs: 2387665 -> 2393604 (0.25%)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=060979a380be0a6149e3e875ee24fdb1e7872821
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 26 10:46:36 2019 -0800
v3d: Fix temporary leaks of temp_registers and when spilling.
On each iteration of successfully spilling a reg, we'd allocate another
copy of temp_registers, and when decrementing thread conut we'd allocate
another copy of the graph. These all got cleaned up on freeing the
compile.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=faf9e40f35ff14045265556acb1f9a2c4ab33c98
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Feb 26 14:40:29 2019 +0000
gitlab-ci: drop job prefixes
It is already obvious whether the job is building a container or running
a mesa build, so let's drop that prefix so that we can see more
information on the screen (eg. in the jobs list on a pipeline page).
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=45809bcb33f273ac0b5c2511e1f2711af2eb1bad
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Mon Mar 4 15:10:55 2019 +0100
tgsi_to_nir: Set correct location for uniforms.
Previously, only the driver_location was set for all variables,
but constants need to use the location field instead. This change
is necessary because the nine state tracker can produce non-packed
constants whose location needs to be explicitly set.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=770faf546d14db6a8eced0da406e48a32fabf551
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Tue Feb 19 10:11:36 2019 +0100
tgsi_to_nir: Improve interpolation modes.
This patch extracts the interpolation mode translation
into a separate function called ttn_translate_interp_mode,
adds support for TGSI_INTERPOLATE_COLOR which was missing,
and also sets the proper interpolation mode to output
variables, which were not set previously.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fb800fd1d1125bdb8cd498cf7b358098337ba73
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 6 03:04:15 2019 -0800
tgsi_to_nir: use sampler variables and derefs
v2: fix is_shadow, is_array and txq
Some drivers (eg. iris) need the presence of sampler variables and derefs
so that they can count them to determine the number of samplers used.
This change also makes the output NIR closer to what glsl_to_nir outputs.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=674045d04b9ebd134b6322a3b944986b4082a3b1
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Fri Feb 8 22:19:14 2019 +0100
tgsi_to_nir: Support FACE and POSITION properly.
Previously, FACE was hard-coded as a sysval, but TTN emulated
it incorrectly. Also, POSITION was not supported when it was
a sysval. This patch fixes these by allowing both of them to
be sysvals or inputs, based on driver capabilities. It also
fixes the TGSI FACE emulation based on the TGSI spec.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f748fa47f84397490bba5c51466f769b18e96f35
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Fri Feb 8 22:11:08 2019 +0100
tgsi_to_nir: Extract ttn_emulate_tgsi_front_face into its own function.
We'll need to use the same logic in other places, so it makes sense to
have a separate function for this.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=840c7d1ebd08785b7fff5efdfc1a7fb2a8ff94b1
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Fri Feb 8 22:15:56 2019 +0100
tgsi_to_nir: Restructure system value loads.
Minor cleanup to the way system value loads work in tgsi_to_nir.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a834447d652ea50864bb6c32f4ff99ac10d39bf
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Tue Mar 5 18:59:47 2019 +0100
tgsi_to_nir: Produce optimized NIR for a given pipe_screen.
With this patch, tgsi_to_nir will output NIR that is tailored to
the given pipe, by reading its capabilities and adjusting the NIR code
to those capabilities similarly to how glsl_to_nir works.
It also adds an optimization loop that brings the output NIR in line
with what glsl_to_nir outputs. This is necessary for the same reason
why glsl_to_nir has its own optimization loop: currently not every
driver does these optimizations yet.
For uses which cannot pass a pipe_screen we also keep a variant
called tgsi_to_nir_noscreen which keeps the old behavior.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Acked-By: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e582e761b7f49d1c0b100289b62442e6295cefef
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Mon Mar 4 13:54:10 2019 +0100
freedreno: Plumb pipe_screen through to irX_tgsi_to_nir.
This patch makes it possible for freedreno to pass a pipe_screen
to tgsi_to_nir. This will be needed when tgsi_to_nir supports reading
pipe capabilities.
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6684e039eba9c2e9602b1cc9d5177f69e478ff46
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Thu Feb 28 10:53:11 2019 +0100
nir: Add multiplier argument to nir_lower_uniforms_to_ubo.
Note that locations can be set in different units, and the multiplier
argument caters to supporting these different units. For example,
st_glsl_to_nir uses dwords (4 bytes) so the multiplier should be 4,
while tgsi_to_nir uses bytes, so the multiplier should be 16.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=909d1f50f3ffc62d5a23669ad0bc8eedb9416af0
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Fri Feb 8 22:36:37 2019 +0100
nir: Move nir_lower_uniforms_to_ubo to compiler/nir.
The nir_lower_uniforms_to_ubo function is useful outside of
mesa/state_tracker, and in fact is needed to produce NIR for
drivers that have the PIPE_CAP_PACKED_UNIFORMS capability.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4dba72c4b35eeb312da232b2f30f067885bc9f07
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Fri Feb 8 09:59:58 2019 +0100
tgsi_to_nir: Split to smaller functions.
Previously, tgsi_to_nir was a single big function, and this patch
intends to make the code easier to understand by splitting it up
to multiple smaller pieces.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Acked-By: Tested-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=950aebbc5317c5a692b522959ad66ea197344121
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Thu Feb 14 01:01:04 2019 +0200
tgsi_to_nir: Make the TGSI IF translation code more readable.
This patch is a minor cleanup that only intends to make the
TGSI IF translation a bit easier to read.
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa076acbc097b9251044f7419760b1d4be56992c
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Thu Feb 14 00:45:47 2019 +0200
tgsi_to_nir: Fix TGSI LIT translation by using flt.
TGSI spec says LIT needs a "greater than" comparison. NIR doesn't have that,
so let's use "less than" and swap the arguments. Previously "greater than or equal"
was used by tgsi_to_nir which is incorrect.
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=28be7b33b959da0eccf8a24b72a441471b7df5f7
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Thu Feb 7 18:01:24 2019 +0100
tgsi_to_nir: Fix the TGSI ARR translation by converting the result to int.
According to the TGSI spec, ARR needs to do a rounding and then
a float-to-integer conversion which was missing. This patch also
makes the rounding a bit more efficient by using nir_fround_even
instead of the previous nir_ffloor+nir_fadd trick.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=317f10bf404b562e1dda79c0636aee86beeccc2f
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Tue Feb 5 18:08:24 2019 +0100
nir: Add ability for shaders to use window space coordinates.
This patch adds a shader_info field that tells the driver to use window
space coordinates for a given vertex shader. It also enables this feature
in radeonsi (the only NIR-capable driver that supported it in TGSI),
and makes tgsi_to_nir aware of it.
Signed-Off-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Andre Heider <a.heider at gmail.com>
Tested-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2780a99ff80cf84f887e8a1dca0079271f90f947
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 22 14:26:26 2019 -0800
v3d: Move the stores for fixed function VS output reads into NIR.
This lets us emit the VPM_WRITEs directly from
nir_intrinsic_store_output() (useful once NIR scheduling is in place so
that we can reduce register pressure), and lets future NIR scheduling
schedule the math to generate them. Even in the meantime, it looks like
this lets NIR DCE some more code and make better decisions.
total instructions in shared programs: 6429246 -> 6412976 (-0.25%)
total threads in shared programs: 153924 -> 153934 (<.01%)
total loops in shared programs: 486 -> 483 (-0.62%)
total uniforms in shared programs: 2385436 -> 2388195 (0.12%)
Acked-by: Ian Romanick <ian.d.romanick at intel.com> (nir)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9dd227a47c8fd767b313827ccbb9e3c67e6b8e7
Author: Eric Anholt <eric at anholt.net>
Date: Sat Feb 23 11:21:26 2019 -0800
v3d: Translate f2i(fround_even) as FTOIN.
This appears to be just what the opcode does. Needed for equivalence when
moving FF VPM stores into NIR.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4f612b4cf84cb5f40ab7eda6075dff89c2b6404
Author: Eric Anholt <eric at anholt.net>
Date: Sat Feb 23 16:17:02 2019 -0800
nir: Improve printing of load_input/store_output variable names.
We were printing only when the channel was exactly the start channel, so
scalarized loads/stores would be missing the name on the rest.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=43f40dc7cb234e007fe612b67cc765288ddf0533
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Feb 12 16:56:24 2019 -0600
anv: Implement VK_EXT_inline_uniform_block
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=61e009d2c4e4dfc071185f9e9c6366bc53168019
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Jan 12 10:58:33 2019 -0600
spirv: Use the same types for resource indices as pointers
We need more space than just a 32-bit scalar and we have to burn all
that space anyway so we may as well expose it to the driver. This also
fixes a subtle bug when UBOs and SSBOs have different pointer types.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f7ee4f8e5b2aa492804367dd64fd5497cb23d1d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Jan 12 10:57:28 2019 -0600
spirv: Use the generic dereference function for OpArrayLength
With the new deref changes, the old pointer_offset version may not be
the right one to call. Just call the generic one and let it sort it
out.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1dbc7e97d3dcb2104b9438d32cace9529575208
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Jan 12 10:32:13 2019 -0600
spirv: Pull offset/stride from the pointer for OpArrayLength
We can't pull it from the variable type because it might be an array of
blocks and not just the one block. While we're here, throw in some
error checking.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: mesa-stable at lists.freedesktop.org
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c520f4dec9cbedd4132143f52411df18f97869e6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Nov 19 14:28:39 2018 -0600
anv: Add a concept of a descriptor buffer
This buffer goes along side the CPU data structure and may contain
pointers, bindless handles, or any other descriptor information.
Currently, all descriptors are size zero and nothing goes in the buffer
but this commit sets up the framework we will need later.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c30fffeec1732c21d600c036f95f8cdb1bb5487
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Feb 12 15:19:57 2019 -0600
anv: Take references to push descriptor set layouts
Technically, descriptor set layouts aren't required to survive past the
function they're passed into so we need to reference them.
Cc: "19.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ab95b849e66f3221d80a67eef2ec6e3730901a8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Feb 12 15:29:19 2019 -0600
anv: Refactor descriptor pushing a bit
Pull the common code out of the two entrypoints into the helper which
fetches the push descriptor set for us. Now that it does more than just
get a thing, call it anv_cmd_buffer_push_descriptor_set.
Cc: "19.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cab064bc10c06eb9fe92e4038d39e7c686fd1ba2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Feb 12 14:02:09 2019 -0600
anv: drop add_var_binding from anv_nir_apply_pipeline_layout.c
It has exactly one caller. Just inline it.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=49cf61c6aa562dba298291c10c365bd2623c2c00
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Nov 24 12:42:39 2018 -0600
anv: Clean up descriptor set layouts
The descriptor set layout code in our driver has undergone many changes
over the years. Some of the fields which were once essential are now
useless or nearly so. The has_dynamic_offsets field was completely
unused accept for the code to set and hash it. The per-stage indices
were only being used to determine if a particular binding had images,
samplers, etc. The fact that it's per-stage also doesn't matter because
that binding should never be accessed by a shader of the wrong stage.
This commit deletes a pile of cruft and replaces it all with a
descriptive bitfield which states what a particular descriptor contains.
This merely describes the data available and doesn't necessarily dictate
how it will be lowered in anv_nir_apply_pipeline_layout.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c50b7c92cd0800e184d2448fbe6b1c5466f5c95
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Feb 6 18:02:30 2019 -0600
anv: Count image param entries rather than images
This is what we're actually storing in the descriptor set and consuming
when we bind surface states. This commit renames image_count to
image_param_count a few places and moves the decision to not count image
params on gen9+ into anv_descriptor_set.c when we build the layout.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3822c7495a096195c81652b5a813b6571ae652d4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Feb 6 17:16:34 2019 -0600
anv: Stop allocating buffer views for dynamic buffers
We emit the surface states for those on-the-fly so we don't need the
buffer view.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c6d410a50d3a7b1e5140b78cfa22dc8b23049c8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Nov 21 18:00:56 2018 -0600
anv: Rework arguments to anv_descriptor_set_write_*
Make them all take a device followed by a set. This is consistent
with how the actual Vulkan entrypoint parameters are laid out.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b7a9e739883f1f25f4046cd8d7eba9787cccc6b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Nov 19 15:15:56 2018 -0600
anv/descriptor_set: Refactor alloc/free of descriptor sets
This commit just puts the free list code together as part of the pool
instead of having it inlined into the descriptor set create code.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd1d22b92edbf98e2ec10c880b2703bfdb0f3b62
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 4 22:11:15 2019 -0800
v3d: Stop treating exec masking specially.
In our backend, the successor edges from the blocks only point to where
QPU control flow goes, not where the notional control flow goes from a
"break" or "continue" modifying the execution mask to resume writing to
some channels later. As a result, this attempt at restricting live ranges
ended up missing the live range of a value where a conditional
break/continue was present in a loop before the later def of a variable.
The previous commit ended up fixing the problem that the flag tried to
solve.
Fixes glsl-vs-loop-continue.shader_test and/or
glsl-vs-loop-redundant-condition.shader_test based on register allocation
results.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6ae666cf5a731118147bb6e88eb520140445e7a
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 4 22:10:33 2019 -0800
v3d: Restrict live intervals to the blocks reachable from any def.
In the backend, we often have condition codes on writes to variables, such
that there's no screening def anywhere and the previous live ranges
algorithm would conclude that the start of the range extends to the start
of the program. However, we do know that the live range can only extend
as early as you can reach from all blocks writing to the variable.
The motivation was that, while we have a couple of hacks to try to promote
conditional writes up to being a def within the block, the exec_mask one
was broken and needed a replacement.
Based on c3c1aa5aeb92 ("intel/fs: Restrict live intervals to the subset
possibly reachable from any definition.").
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf79d62f90a857c92e45f3ab6ba363b0688ce0f0
Author: Andres Gomez <agomez at igalia.com>
Date: Tue Mar 5 13:55:17 2019 +0200
gitlab-ci: install distro's ninja
Ubuntu Bionic is shipping ninja 1.8.2. Therefore, we do not need to
download v1.6.0 manually any more.
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2a148692b4d728e481b60a503e21931f9cf43f0
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Mar 4 14:25:08 2019 +0100
radv: properly align the fence and EOP bug VA on GFX9
If alignement is 0, offets returned by
radv_cmd_buffer_upload_alloc() are always 0. These two
virtual addresses were pointing at the same location.
Cc: 18.3 19.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2eb0905ffa133129a65d20e098f121302944a753
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Mar 5 10:45:00 2019 +0100
radv: allocate enough space in cmdbuf when starting a subpass
This fixes some CTS crashes with:
dEQP-VK.renderpass2.suballocation.attachment_write_mask.attachment_count_8.start_index_*
Ideally, we should check cmd_buffer->cs->max_dw because there is
likely enough space (the internal clear draws allocate space), but
keep that way for consistency.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=31d302ae51a2c07d17a994778193f8ba48f080a6
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Mar 5 13:18:28 2019 +0000
vulkan: import vk_layer.h from Khronos
Instead of relying on the system having it (and the right version).
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcc4bfc8e80da5dc4c6ee44f791f2112dac208d1
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 15:26:08 2019 +0000
egl: fix libdrm-less builds
This function was never used, and isn't properly guarded by HAVE_LIBDRM,
breaking the build on systems that don't have libdrm.
Let's just remove it.
Fixes: 7552fcb7b9b98392e6a8 "egl: add base EGL_EXT_device_base implementation"
Reported-by: Timo Aaltonen <tjaalton at debian.org>
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Acked-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e37ea1e0d398e9f139b9a9f15585272cfa706cff
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Mar 5 12:20:53 2019 +0000
vulkan: import missing file from Khronos
Fixes: 114c4aa0c84fc6d00407 "vulkan: update headers/registry to 1.1.102"
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=91cc6fcbb050423823ff4262cf860a34d20f504e
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 15:08:56 2019 +0000
util: #define PATH_MAX when undefined (eg. Hurd)
Cc: Timo Aaltonen <tjaalton at debian.org>
Cc: James Clarke <jrtc27 at debian.org>
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe205818c243528924c1beca5dfeef5f81495401
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 12:20:56 2019 +0000
radv: use the platform defines in vk.xml instead of hard-coding them
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d4238d26c5de4a0f7a5c225c77fd29db29672ee
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 12:20:31 2019 +0000
anv: use the platform defines in vk.xml instead of hard-coding them
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e21c201c9684fa5b588735c2edeb5985c2a2f795
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Mar 4 17:36:10 2019 +0000
anv: update supported patch version
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bb8768b9d62b616035104485ff05a9d9d2c7546
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Feb 22 08:54:13 2019 +0200
anv: toggle on support for VK_EXT_ycbcr_image_arrays
We already propagate coord_components correctly and did not have
layer restrictions for ycbcr formats.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=114c4aa0c84fc6d00407192d283f30dc2582621e
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Mar 4 17:40:08 2019 +0000
vulkan: update headers/registry to 1.1.102
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33bf3d510c98a22706eb25815f1214d2e1a0e868
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Feb 20 09:18:39 2019 +0200
anv: retain the is_array state in create_plane_tex_instr_implicit
This does not seem to fix anything ATM but is the right thing todo.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Fixes: f3e91e78a33775 ("anv: add nir lowering pass for ycbcr textures")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1ee4ab3dcfb73e4975e02e70cc831b5b607d2e0
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Thu Feb 14 17:22:00 2019 +0000
meson: avoid going back up the tree with include_directories()
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Dylan Baker <dylan at pnwbakers.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dca36d5516d0fdaf012b4476975c5d585c2d1a09
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jul 9 23:03:44 2017 -0700
i965: Implement threaded GL support.
Now i965 supports mesa_glthread=true like Gallium drivers do.
According to Markus (degasus), the Citra emulator now runs ~30% faster.
Emmanuel (linkmauve) also reported that the Dolphin emulator improved
by 2.8x on one game. (Both of those still need to be added to drirc.)
An Intel Mesa CI run with mesa_glthread=true appears to be happy.
Bioshock Infinite's benchmark mode seems to be around 15-20% faster
on my Skylake GT4 at 1920x1080.
Tested-by: Markus Wick <markus at selfnet.de>
Tested-by: Emmanuel Gil Peyrot <linkmauve at linkmauve.fr>
Tested-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0010d0348aa56e1097093628b1c1ec062c43c2fa
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Mar 2 01:33:39 2019 -0600
anv/pipeline: Drop anv_fill_binding_table
We zero out the prog data anyway and, now that bias is always zero, this
function is accomplishing nothing.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=65ee5cc0da39a5be6171a49d9b2408510ae69062
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Feb 23 13:34:11 2019 -0600
anv: Use an actual binding for gl_NumWorkgroups
This commit moves our handling of gl_NumWorkgroups over to work like our
handling of other special bindings in the Vulkan driver. We give it a
magic descriptor set number and teach emit_binding_tables to handle it.
This is better than the bias mechanism we were using because it allows
us to do proper accounting through the bind map mechanism.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c96120b5ce158fea28d751d8a55b5e4d80df4f3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Feb 8 17:51:24 2019 -0600
intel,nir: Lower TXD with min_lod when the sampler index is not < 16
When we have a larger sampler index, we get into the "high sampler"
scenario and need an instruction header. Even in SIMD8, this pushes the
instruction over the sampler message size maximum of 11 registers.
Instead, we have to lower TXD to TXL.
Fixes: cb98e0755f8d "intel/fs: Support min_lod parameters on texture..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca295ddbfb414a526d3bab7daf93fffbbc417c6e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Feb 27 00:12:01 2019 -0600
spirv: OpImageQueryLod requires a sampler
No idea how this fell through the cracks besides the fact that the
sampler bound at 0 almost always works and the CTS isn't amazing. In
any case, this appears to have been broken for almost forever.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: mesa-stable at lists.freedesktop.org
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5049fbddb4687799a10eb585c8789afa0d080535
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Mar 1 14:01:08 2019 -0600
anv: Count surfaces for non-YCbCr images in GetDescriptorSetLayoutSupport
We were accidentally not counting those surfaces
Fixes: ddc4069122 "anv: Implement VK_KHR_maintenance3"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=58bcebd987b7c4e7d741f42699d34b8189ab9e79
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date: Mon Feb 25 14:56:29 2019 -0800
spirv: Allow [i/u]mulExtended to use new nir opcode
Use new nir opcode nir_[i/u]mul_2x32_64 and extract lower and higher 32
bits as needed instead of emitting mul and mul_high.
v2: Surround the switch case with curly braces (Jason Ekstrand)
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=47ec9bdc604cb91af5acdb8522972ede7872cf71
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date: Mon Feb 25 11:43:53 2019 -0800
nir/algebraic: Optimize low 32 bit extraction
Optimize a situation where we only need lower 32 bits from 64 bit
result.
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Suggested-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d8994a63b546a5b2dc4feb5bd98a84ee853d6af
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date: Wed Feb 27 14:02:54 2019 -0800
glsl: [u/i]mulExtended optimization for GLSL
Optimize mulExtended to use 32x32->64 multiplication.
Drivers which are not based on NIR, they can set the
MUL64_TO_MUL_AND_MUL_HIGH lowering flag in order to have same old
behavior.
v2: Add missing condition check (Jason Ekstrand)
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Suggested-by: Matt Turner <Matt Turner <mattst88 at gmail.com>
Suggested-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e551040c602d392019e68f54d9a3a310d2a937a3
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date: Thu Feb 14 23:08:39 2019 -0800
nir/glsl: Add another way of doing lower_imul64 for gen8+
On Gen 8 and 9, "mul" instruction supports 64 bit destination type. We
can reduce our 64x64 int multiplication from 4 instructions to 3.
Also instead of emitting two mul instructions, we can emit single mul
instuction and extract low/high 32 bits from 64 bit result for
[i/u]mulExtended
v2: 1) Allow lower_mul_high64 to use new opcode (Jason Ekstrand)
2) Add lower_mul_2x32_64 flag (Matt Turner)
3) Remove associative property as bit size is different (Connor
Abbott)
v3: Fix indentation and variable naming convention (Jason Ekstrand)
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d363d440f261fbadc1db3c17acc514b7130d505
Author: Axel Davy <davyaxel0 at gmail.com>
Date: Fri Feb 22 20:45:51 2019 +0100
st/nine: Ignore multisample quality level if no ms
Apparently instead of returning error when passing
a quality level different than 0 for
D3DMULTISAMPLE_NONE, we should pass.
Fixes: https://github.com/iXit/Mesa-3D/issues/340
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Axel Davy <davyaxel0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=86666f051e0cae96f2596cac05e3c3f394744149
Author: Axel Davy <davyaxel0 at gmail.com>
Date: Wed Jan 2 22:13:12 2019 +0100
st/nine: Ignore window size if error
Check GetWindowInfo and ignore the computed sizes
if there is an error.
Fixes a regression caused by earlier commit when
using old wine gallium nine patches.
Should also address a crash at window destruction.
Related issues:
https://github.com/iXit/Mesa-3D/issues/331
https://github.com/iXit/Mesa-3D/issues/332
Cc: mesa-stable at lists.freedesktop.org
Fixes: 2318ca68bbe ("st/nine: Handle window resize when a presentation
buffer is used")
Signed-off-by: Axel Davy <davyaxel0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec0f465bc5f02c93aeb4193db8b5bd90a254b080
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Sat Mar 2 23:38:27 2019 +0100
android: anv: fix libexpat shared dependency
Fixes undefined reference building errors for XML_* functions
Signed-off-by: Mauro Rossi <issor.oruam at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Cc: "19.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=14e7e26a0991e7f9b1d20147f04a43bb4cc3f824
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Mon Mar 4 10:34:08 2019 +0100
android: anv: fix generated files depedencies (v2)
Fix anv_extrypoints.{c,h} and anv_extensions.{c,h} missing dependencies
Rename the variable labels according to targets and python scripts
Align the building rules as per Automake for simplification
Fixes building errors during rebuils due to missing dependencies
(v2) Fixed a missing $(VULKAN_API_XML) reference
Fixes: 9a508b7 ("android: anv/extensions: fix generated sources build")
Fixes: dd088d4bec7 ("anv/extensions: Generate a header file with extension tables")
Signed-off-by: Mauro Rossi <issor.oruam at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
Cc: "19.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2369e133c052f85ca8ceea6bb8a4d8457809a42
Author: Brian Paul <brianp at vmware.com>
Date: Sat Mar 2 11:26:44 2019 -0700
st/wgl: init a variable to silence MinGW warning
MinGW release build says 'value' may be used before being initialized.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66ba12973bcbe35f7c41c32270f92073e946b1d5
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 1 13:56:18 2019 -0700
svga: silence array out of bounds warning
MinGW release build complains about a possible out-of-bounds
array access. Test i < 4 to silence it.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=999db9ac51b312f8d18f5a39025f1b0dabddd073
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 1 13:55:30 2019 -0700
svga: init fill variable to avoid compiler warning
MinGW release builds warns about use of a possbily uninitialized
variable here.
Reviewed-by: Neha Bhende <bhenden at vmware.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b07a221a4acd5fc80f9a5be56b4484e37c39e80
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 28 12:01:02 2019 -0700
st/mesa: whitespace fixes in st_texture.h
Trivial.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d74932dfea142acce527f880a5c42c6ab8bd0e40
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 28 11:59:16 2019 -0700
st/mesa: line wrapping, whitespace fixes in st_cb_texture.c
Trivial.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc91c2698e9f2ac739b0b57a97cf340e0c766760
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 28 11:56:31 2019 -0700
st/mesa: whitespace fixes in st_sampler_view.c
Replace tabs w/ spaces. 80-column wrapping.
Trivial.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=610758d3e5402709b9b92cfa88f72b092b13f236
Author: Gurchetan Singh <gurchetansingh at chromium.org>
Date: Fri Mar 1 18:58:16 2019 -0800
egl/sl: also allow virtgpu to fallback to kms_swrast
virtio-gpu fallbacks to software rendering when 3D features
are unavailable since 6c5ab, and kms_swrast is more
feature complete than swrast.
v2: Add comment (Emil)
Reviewed-by: Eric Engestrom <eric at engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=904a0552aabf0624f1d7507b89d8a9a7bdd3bad5
Author: Mathias Fröhlich <mathias.froehlich at web.de>
Date: Tue Feb 26 06:39:05 2019 +0100
st/mesa: Invalidate the gallium array atom only if needed.
Now that the buffer object usage history tracks if it is
being used as vertex buffer object, we can restrict setting
the ST_NEW_VERTEX_ARRAYS bit to dirty on glBufferData calls to
buffers that are potentially used as vertex buffer object.
Also put a note that the same could be done for index arrays
used in indexed draws.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e727f8c8b814b9c36d4a8b52829c2bf7281765be
Author: Mathias Fröhlich <mathias.froehlich at web.de>
Date: Fri Dec 21 18:41:27 2018 +0100
mesa: Track buffer object use also for VAO usage.
We already track the usage history for buffer objects
in a lot of aspects. Add GL_ARRAY_BUFFER and
GL_ELEMENT_ARRAY_BUFFER to gl_buffer_object::UsageHistory.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e787904d0a5c0dfde509a03f31f7a0c6f2993c3
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Mar 1 18:28:02 2019 +0100
rav: use 32_AR instead of 32_ABGR when alpha coverage is required
This export format is faster. Seems to improve performance in
Wreckfest.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=72981c92ce806d48d1d7955a119abc38968fd2c7
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Wed Feb 27 04:33:13 2019 +0000
panfrost: List primitive restart enable bit
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b5cda137f84ebd73de462d19ca9cb74b280bb38
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Wed Feb 27 05:40:55 2019 +0000
panfrost/midgard: Preview for data hazards
If a selected unit causes a data hazard, the whole block gets cut short.
So, we preview for data hazards _while_ selecting units.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Tested-by: Tomeu Vizoso <tomeu.vizoso at collabora.com
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=93eeba623bd3e9a1b106e82f40147681c3011535
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Wed Feb 27 05:32:16 2019 +0000
panfrost/midgard: Promote smul to vmul
smul comes first in the pipeline, before vmul. Until we have a full
instruction scheduler, it's better to have vmul prioritized to maximize
bundle size.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Tested-by: Tomeu Vizoso <tomeu.vizoso at collabora.com
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=25bbb44dce347b37caa5efdb7d5dfccbe593427e
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Mon Mar 4 05:01:45 2019 +0000
panfrost: Flush with offscreen rendering
This special-case was needlessly added and breaks purely offscreen
rendering (when there is no scanout involved)
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f7460297bcb07605f05e91236346aeedd0f0c16
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Wed Feb 27 02:06:29 2019 +0000
panfrost/midgard: Don't force constant on VLUT
Previously, we forced a #0 inline constant tacked on for the lut
instructions to mirror the blob's behaviour, which caused some
suboptimal codegen due to our constant inlining implementation. Instead,
just don't force a constant at all.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Tested-by: Tomeu Vizoso <tomeu.vizoso at collabora.com
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c351cc4e94410e76ef0512d4bc503ef90adf3370
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Wed Feb 27 00:30:59 2019 +0000
panfrost: Cleanup cruft related to clears
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40ffee4448835e04d139657aafdb5919aa5af941
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Tue Feb 26 23:51:34 2019 +0000
panfrost: Decouple Gallium clear from FBD clear
The operations of gallium->clear() and the hardware callbacks are
fundamentally independent. This routine decouples them by routing shared
information via panfrost_job, allowing the hardware half to be deferred
to the fragment job generation.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59c9623d0a75d5201ad48351af26aad1bc0b7073
Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date: Mon Feb 25 05:32:16 2019 +0000
panfrost: Import job data structures from v3d
At the moment, Panfrost state is ad hoc, which creates issues for FBOs.
This commit imports the skeleton of the v3d_job structure as
panfrost_job, in preparation for refactors to organize this state.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4eec3a2a3652317f8e0fa97e0730c297bde8241a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Feb 22 01:13:39 2019 -0500
glsl: fix recording of variables for XFB in TCS shaders
This is purely for conformance, since it's not actually possible to do
XFB on TCS output varyings. However we do have to make sure we record
the names correctly, and this removes an extra level of array-ness from
the names in question.
Fixes KHR-GL45.tessellation_shader.single.xfb_captures_data_from_correct_stage
v2: Add comment to the new program_resource_visitor::process function.
(Ilia Mirkin)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108457
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: 19.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf1f49482d677e562993543cd9a9367597ce3ccc
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Wed Nov 21 18:23:03 2018 +0100
glsl: TCS outputs can not be transform feedback candidates on GLES
Avoids regression on:
KHR-GLES*.core.tessellation_shader.single.xfb_captures_data_from_correct_stage
that is uncovered by the following patch.
"glsl: fix recording of variables for XFB in TCS shaders"
v2: Rebased over glsl: fix recording of variables for XFB in TCS shaders
v3: Move this patch before "glsl: fix recording of variables for XFB in TCS
shaders" to avoid temporal regressions. (Illia Mirkin)
Cc: 19.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc7173b4387182f854cb5c9d4f9575419b946e11
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Wed Nov 21 19:22:05 2018 +0100
glsl: fix typos in comments "transfor" -> "transform"
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3214f20914134df07b070f471c0ca2d610ed3b81
Author: Gert Wollny <gert.wollny at collabora.com>
Date: Mon Feb 25 19:12:07 2019 +0100
mesa: Expose EXT_texture_query_lod and add support for its use shaders
EXT_texture_query_lod provides the same functionality for GLES like
the ARB extension with the same name for GL.
v2: Set ES 3.0 as minimum GLES version as required by the extension
Signed-off-by: Gert Wollny <gert.wollny at collabora.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7dc2f4788288ec9c7ab63e37fdea750c08503eca
Author: Greg V <greg at unrelenting.technology>
Date: Sun Dec 24 19:55:46 2017 +0300
util: emulate futex on FreeBSD using umtx
Obtained from: FreeBSD ports
Acked-by: Emil Velikov <emil.velikov at collabora.com>
Acked-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=00f838fa730f5c765902fe2e5ce9754df5276e91
Author: Rob Clark <robdclark at gmail.com>
Date: Wed Feb 27 09:56:18 2019 -0500
freedreno/ir3: track register pressure in sched
Not a perfect solution, and the "pressure" target is hard-coded. But it
doesn't really seem to much in the common case, and avoids exploding
register usage in dEQP ssbo tests.
So this should serve as a stop-gap solution until I have time to re-
write the scheduler.
Hurts slightly in instruction count, but gains (reduces) slightly the
register usage in shader-db. Fixes ~150 dEQP-GLES31.functional.ssbo.*
that were failing due to RA fail.
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a5f2d9444879dc4c8b2b1f192b2a667a1278a2b
Author: Rob Clark <robdclark at gmail.com>
Date: Sat Nov 24 12:18:08 2018 -0500
freedreno/ir3: add Sethi–Ullman numbering pass
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8e351ee3af63aad28d572cd5efb307a8e65e03d
Author: Rob Clark <robdclark at gmail.com>
Date: Wed Feb 27 15:57:23 2019 -0500
freedreno/ir3: include nopN in expanded instruction count
Signed-off-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb4e3e3ef6e47811303ad3413a4ab2048696a6f6
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jan 10 16:24:57 2019 +1000
st/mesa: add support for lowering fp64/int64 for nir drivers
This might enough for iris and possible r600 (when it gets NIR)
This appears to work for iris.
v2:
* change cap return so DOUBLES == 2 means sw emu
v3:
* Refactor using int64/doubles lowering options which were added
into nir options
* Remove DOUBLES == 2 added in v2
[jordan: Remove "2" value on PIPE_CAP_DOUBLES]
[jordan: Use lowering options added to nir options]
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7de056e1a9661273ba5055d094f17cf0b9ca92f3
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Feb 25 23:26:16 2019 -0800
scons: Generate float64_glsl.h for glsl_to_nir fp64 lowering
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=10c5579921979c944978b477db8bdd639d3c9559
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Feb 25 17:17:29 2019 -0800
intel/compiler: Move int64/doubles lowering options
Instead of calculating the int64 and doubles lowering options each
time a shader is preprocessed, save and use the values in
nir_shader_compiler_options.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=31b35916dd29ac4578f061bdeac873cea5f91104
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Feb 25 17:13:48 2019 -0800
nir: Add int64/doubles options into nir_shader_compiler_options
This will allow the options to be visible under nir_shader->options,
which will allow the gallium state_tracker to use the driver preferred
settings during glsl_to_nir.
Suggested-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bae0c3675174b63c7d7e25556266027b2d4f2b87
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Mar 1 14:41:59 2019 -0800
nir/algebraic: Optimize away an fsat of a b2f
The b2f can only produce 0.0 or 1.0, so the fsat does nothing.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1d56f5f9afceab732e46c43010738c4936fb9b9
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Mar 1 14:39:14 2019 -0800
intel/fs: Don't assert on b2f with a saturate modifier
This ran afoul of Iris's use of nir_lower_clamp_color_outputs which
applies fsat() before writes to vertex shader color outpus.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Fixes: 7725d609387 ("intel/fs: Emit better code for b2f(inot(a)) and b2i(inot(a))")
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=32ffd90002b04bff20a587e5d2f31fe79af1a4f2
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Sat Feb 23 23:27:17 2019 +0000
anv: add support for INTEL_DEBUG=bat
As requested by Ken ;)
v2: Also decode simple batches (Caio)
Fix u_vector usage issues (Lionel)
v3: Make binding/instruction/state/surface available (Lionel)
v4: Going through device pools for simple batches (Lionel)
Centralize search BO callbacks into anv_device.c (Lionel)
v5: Clear decoded batch buffer var after use (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1122f78b765ecbb5702b5c2e2bf4a03fb83d778
Author: Eric Anholt <eric at anholt.net>
Date: Fri Mar 1 12:48:51 2019 -0800
v3d: Fix build of NEON code with Mesa's cflags not targeting NEON.
v3d may be built as part of a set of drivers in a system not requiring
NEON, but we know V3D devices will be paired with CPUs with NEON so we
should be able to use this asm.
Fixes: 0c05198d6b5b ("v3d: Always enable the NEON utile load/store code.")
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0148bbcfdc0870fc60688ab6ac4ccb33545a181
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Feb 15 14:43:30 2018 -0800
intel/compiler: Add commas on final values of compaction table arrays
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecc9ffa778b5d6bb8ecb388607c60575c5edba9c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Feb 22 16:47:06 2019 -0800
nir/algebraic: Replace a-fract(a) with floor(a)
I noticed this while looking at a shader that was affected by Tim's
"more loop unrolling" series.
In review, Tim Arceri asked:
> Why the hurt on Gen6+ is this something that should be in the late
> optimisations pass?
As far as I can tell, it's just because our scheduler is terrible. In
all the fragment shaders that I looked at (some hurt shaders were from
other stages), only one of the SIMD8 or SIMD16 version would be hurt.
In many of those case, the other SIMD width is improved (e.g.,
shaders/closed/steam/brutal-legend/3990.shader_test).
Often it looks like the scheduler decides to differently schedule a SEND
the occurs somewhere early in the shader. Once that happens, everything
is different.
I looked at one vertex shader that was hurt (from Goat Simulator). In
that case, both the floor and fract are used. The optimization
eliminates the add, and it should allow better scheduling. In the area
of the FRC and RNDD instructions, the scheduler does the right thing.
However, later in the shader a MAD and and ADD get scheduled
differently, and that makes it slightly worse.
In light of this, I tried adding some "is_used_once" mark-up, and that
did not fix all the cycles regressions. It also did a lot more harm
than good on SKL (helped 82 vs. hurt 241).
All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 15437001 -> 15435259 (-0.01%)
instructions in affected programs: 213651 -> 211909 (-0.82%)
helped: 988
HURT: 0
helped stats (abs) min: 1 max: 27 x̄: 1.76 x̃: 1
helped stats (rel) min: 0.15% max: 11.54% x̄: 1.14% x̃: 0.59%
95% mean confidence interval for instructions value: -1.89 -1.63
95% mean confidence interval for instructions %-change: -1.23% -1.05%
Instructions are helped.
total cycles in shared programs: 383007378 -> 382997063 (<.01%)
cycles in affected programs: 1650825 -> 1640510 (-0.62%)
helped: 679
HURT: 302
helped stats (abs) min: 1 max: 348 x̄: 23.39 x̃: 14
helped stats (rel) min: 0.04% max: 28.77% x̄: 1.61% x̃: 0.98%
HURT stats (abs) min: 1 max: 250 x̄: 18.43 x̃: 7
HURT stats (rel) min: 0.04% max: 25.86% x̄: 1.41% x̃: 0.53%
95% mean confidence interval for cycles value: -13.05 -7.98
95% mean confidence interval for cycles %-change: -0.86% -0.50%
Cycles are helped.
Iron Lake and GM45 had similar results. (GM45 shown)
total instructions in shared programs: 5043616 -> 5043010 (-0.01%)
instructions in affected programs: 119691 -> 119085 (-0.51%)
helped: 432
HURT: 0
helped stats (abs) min: 1 max: 27 x̄: 1.40 x̃: 1
helped stats (rel) min: 0.10% max: 8.11% x̄: 0.66% x̃: 0.39%
95% mean confidence interval for instructions value: -1.58 -1.23
95% mean confidence interval for instructions %-change: -0.72% -0.59%
Instructions are helped.
total cycles in shared programs: 128139812 -> 128135762 (<.01%)
cycles in affected programs: 3829724 -> 3825674 (-0.11%)
helped: 602
HURT: 0
helped stats (abs) min: 2 max: 486 x̄: 6.73 x̃: 6
helped stats (rel) min: 0.02% max: 4.85% x̄: 0.19% x̃: 0.10%
95% mean confidence interval for cycles value: -8.40 -5.05
95% mean confidence interval for cycles %-change: -0.22% -0.16%
Cycles are helped.
Reviewed-by: Elie Tournier <tournier.elie at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1edf67fc3f6b944935506146de02348afa1003ff
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Dec 3 12:06:50 2018 -0800
intel/fs: Generate if instructions with inverted conditions
Per-platform results were all over the place, so I have included all the
results here. There is an important note at the bottom of the commit
message.
Skylake
total instructions in shared programs: 15184683 -> 15184679 (<.01%)
instructions in affected programs: 2786 -> 2782 (-0.14%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.05% max: 0.84% x̄: 0.44% x̃: 0.44%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.96% 0.07%
Inconclusive result (%-change mean confidence interval includes 0).
total cycles in shared programs: 370961367 -> 370961173 (<.01%)
cycles in affected programs: 205867 -> 205673 (-0.09%)
helped: 5
HURT: 1
helped stats (abs) min: 1 max: 149 x̄: 39.60 x̃: 16
helped stats (rel) min: 0.02% max: 1.05% x̄: 0.45% x̃: 0.55%
HURT stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
HURT stats (rel) min: 0.03% max: 0.03% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -93.01 28.34
95% mean confidence interval for cycles %-change: -0.82% 0.08%
Inconclusive result (value mean confidence interval includes 0).
Broadwell
total instructions in shared programs: 15465366 -> 15465362 (<.01%)
instructions in affected programs: 2799 -> 2795 (-0.14%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.04% max: 0.84% x̄: 0.44% x̃: 0.44%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.96% 0.07%
Inconclusive result (%-change mean confidence interval includes 0).
total cycles in shared programs: 410938419 -> 410938531 (<.01%)
cycles in affected programs: 566028 -> 566140 (0.02%)
helped: 18
HURT: 17
helped stats (abs) min: 1 max: 16 x̄: 3.50 x̃: 1
helped stats (rel) min: <.01% max: 1.05% x̄: 0.13% x̃: <.01%
HURT stats (abs) min: 1 max: 12 x̄: 10.29 x̃: 12
HURT stats (rel) min: <.01% max: 0.16% x̄: 0.08% x̃: 0.09%
95% mean confidence interval for cycles value: 0.31 6.09
95% mean confidence interval for cycles %-change: -0.10% 0.05%
Inconclusive result (%-change mean confidence interval includes 0).
Haswell
total instructions in shared programs: 13749760 -> 13749759 (<.01%)
instructions in affected programs: 2241 -> 2240 (-0.04%)
helped: 1
HURT: 0
total cycles in shared programs: 385398913 -> 385398363 (<.01%)
cycles in affected programs: 554914 -> 554364 (-0.10%)
helped: 31
HURT: 1
helped stats (abs) min: 1 max: 453 x̄: 18.00 x̃: 6
helped stats (rel) min: <.01% max: 0.25% x̄: 0.03% x̃: 0.05%
HURT stats (abs) min: 8 max: 8 x̄: 8.00 x̃: 8
HURT stats (rel) min: 0.06% max: 0.06% x̄: 0.06% x̃: 0.06%
95% mean confidence interval for cycles value: -45.88 11.51
95% mean confidence interval for cycles %-change: -0.05% -0.02%
Inconclusive result (value mean confidence interval includes 0).
Ivy Bridge
total cycles in shared programs: 180663626 -> 180663881 (<.01%)
cycles in affected programs: 472350 -> 472605 (0.05%)
helped: 15
HURT: 30
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
HURT stats (abs) min: 8 max: 10 x̄: 9.00 x̃: 9
HURT stats (rel) min: 0.06% max: 0.14% x̄: 0.10% x̃: 0.10%
95% mean confidence interval for cycles value: 4.21 7.12
95% mean confidence interval for cycles %-change: 0.05% 0.08%
Cycles are HURT.
Sandy Bridge
total cycles in shared programs: 154568664 -> 154569225 (<.01%)
cycles in affected programs: 356486 -> 357047 (0.16%)
helped: 1
HURT: 31
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.02% max: 0.02% x̄: 0.02% x̃: 0.02%
HURT stats (abs) min: 4 max: 33 x̄: 18.16 x̃: 8
HURT stats (rel) min: 0.05% max: 0.23% x̄: 0.14% x̃: 0.10%
95% mean confidence interval for cycles value: 12.19 22.87
95% mean confidence interval for cycles %-change: 0.10% 0.16%
Cycles are HURT.
Iron Lake
total instructions in shared programs: 8206589 -> 8206565 (<.01%)
instructions in affected programs: 3024 -> 3000 (-0.79%)
helped: 12
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.75% max: 0.83% x̄: 0.80% x̃: 0.80%
95% mean confidence interval for instructions value: -2.00 -2.00
95% mean confidence interval for instructions %-change: -0.82% -0.77%
Instructions are helped.
total cycles in shared programs: 187657428 -> 187656228 (<.01%)
cycles in affected programs: 95748 -> 94548 (-1.25%)
helped: 12
HURT: 0
helped stats (abs) min: 80 max: 120 x̄: 100.00 x̃: 100
helped stats (rel) min: 1.00% max: 1.66% x̄: 1.27% x̃: 1.21%
95% mean confidence interval for cycles value: -113.27 -86.73
95% mean confidence interval for cycles %-change: -1.43% -1.11%
Cycles are helped.
GM45
total instructions in shared programs: 5037569 -> 5037557 (<.01%)
instructions in affected programs: 1521 -> 1509 (-0.79%)
helped: 6
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.75% max: 0.83% x̄: 0.79% x̃: 0.79%
95% mean confidence interval for instructions value: -2.00 -2.00
95% mean confidence interval for instructions %-change: -0.83% -0.75%
Instructions are helped.
total cycles in shared programs: 128101478 -> 128100758 (<.01%)
cycles in affected programs: 52746 -> 52026 (-1.37%)
helped: 6
HURT: 0
helped stats (abs) min: 120 max: 120 x̄: 120.00 x̃: 120
helped stats (rel) min: 1.16% max: 1.66% x̄: 1.41% x̃: 1.41%
95% mean confidence interval for cycles value: -120.00 -120.00
95% mean confidence interval for cycles %-change: -1.70% -1.12%
Cycles are helped.
This change has almost no effect right now. However, removing this
patch (but leaving the patch "nir/algebraic: Replace a bcsel of a b2f
with a b2f(!(a || b))") after adding a patch that removes !(a < b) -> (a
>= b) optimizations (like
https://patchwork.freedesktop.org/patch/264787/) has the following
results on Skylake:
Skylake
total instructions in shared programs: 15071022 -> 15089710 (0.12%)
instructions in affected programs: 1022219 -> 1040907 (1.83%)
helped: 1
HURT: 3937
helped stats (abs) min: 41 max: 41 x̄: 41.00 x̃: 41
helped stats (rel) min: 1.01% max: 1.01% x̄: 1.01% x̃: 1.01%
HURT stats (abs) min: 1 max: 256 x̄: 4.76 x̃: 4
HURT stats (rel) min: 0.05% max: 11.18% x̄: 2.59% x̃: 2.60%
95% mean confidence interval for instructions value: 4.56 4.93
95% mean confidence interval for instructions %-change: 2.54% 2.64%
Instructions are HURT.
total cycles in shared programs: 369777134 -> 370092923 (0.09%)
cycles in affected programs: 17516573 -> 17832362 (1.80%)
helped: 115
HURT: 3624
helped stats (abs) min: 1 max: 1721 x̄: 81.18 x̃: 28
helped stats (rel) min: <.01% max: 10.74% x̄: 1.24% x̃: 0.65%
HURT stats (abs) min: 1 max: 12640 x̄: 89.71 x̃: 54
HURT stats (rel) min: <.01% max: 28.24% x̄: 4.72% x̃: 4.52%
95% mean confidence interval for cycles value: 75.21 93.71
95% mean confidence interval for cycles %-change: 4.43% 4.64%
Cycles are HURT.
total spills in shared programs: 9450 -> 9442 (-0.08%)
spills in affected programs: 166 -> 158 (-4.82%)
helped: 2
HURT: 0
total fills in shared programs: 21115 -> 21094 (-0.10%)
fills in affected programs: 438 -> 417 (-4.79%)
helped: 2
HURT: 0
LOST: 1
GAINED: 0
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d40640efe8a6f3cc1d86870678ae1f89264354ec
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Dec 3 14:41:07 2018 -0800
nir/algebraic: Replace a bcsel of a b2f sources with a b2f(!(a || b))
I have not investigated the result of doing this during code
generation. That should be possible, but it would be a bit more
effort.
All Gen6+ platforms had nearly identical results. (Skylake shown)
total cycles in shared programs: 370961508 -> 370961367 (<.01%)
cycles in affected programs: 5174 -> 5033 (-2.73%)
helped: 2
HURT: 0
Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8206587 -> 8206589 (<.01%)
instructions in affected programs: 1325 -> 1327 (0.15%)
helped: 0
HURT: 2
total cycles in shared programs: 187657422 -> 187657428 (<.01%)
cycles in affected programs: 11566 -> 11572 (0.05%)
helped: 0
HURT: 2
This change has almost no effect right now. However, removing this
patch (but leaving the patch "intel/fs: Generate if instructions with
inverted conditions") after adding a patch that removes !(a < b) -> (a
>= b) optimizations (like
https://patchwork.freedesktop.org/patch/264787/) has the following
results on Skylake:
Skylake
total instructions in shared programs: 15071804 -> 15071806 (<.01%)
instructions in affected programs: 640 -> 642 (0.31%)
helped: 0
HURT: 2
total cycles in shared programs: 369914348 -> 369916569 (<.01%)
cycles in affected programs: 27900 -> 30121 (7.96%)
helped: 4
HURT: 15
helped stats (abs) min: 2 max: 112 x̄: 30.00 x̃: 3
helped stats (rel) min: 0.28% max: 12.28% x̄: 3.34% x̃: 0.40%
HURT stats (abs) min: 2 max: 758 x̄: 156.07 x̃: 81
HURT stats (rel) min: 0.20% max: 74.30% x̄: 16.29% x̃: 16.91%
95% mean confidence interval for cycles value: 12.68 221.11
95% mean confidence interval for cycles %-change: 3.09% 21.23%
Cycles are HURT.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7725d609387a8165ccb71e2d9e0221d9248b1729
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Dec 3 15:53:36 2018 -0800
intel/fs: Emit better code for b2f(inot(a)) and b2i(inot(a))
Since Boolean values are either -1 (true) or 0 (false), b2f(inot(a))
maps -1 => 0.0 and 0 => 1.0. This is equivalent to 1.0 +
float(boolBitsToInt(a)). On Intel GPUs, ADD is one of the few
instructions that can type-convert during write to destination, so we
can achieve this in a single instruction:
add g47F, g26D, 1D
v2: Fix swizzles.
v3: Fix typos in comments. Noticed by Ken.
All Gen6+ platforms had similar results. (Skylake shown)
Skylake
total instructions in shared programs: 15185583 -> 15184683 (<.01%)
instructions in affected programs: 239389 -> 238489 (-0.38%)
helped: 899
HURT: 1
helped stats (abs) min: 1 max: 2 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.15% max: 1.85% x̄: 0.49% x̃: 0.44%
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.09% max: 0.09% x̄: 0.09% x̃: 0.09%
95% mean confidence interval for instructions value: -1.01 -0.99
95% mean confidence interval for instructions %-change: -0.51% -0.48%
Instructions are helped.
total cycles in shared programs: 370964249 -> 370961508 (<.01%)
cycles in affected programs: 1487586 -> 1484845 (-0.18%)
helped: 420
HURT: 268
helped stats (abs) min: 1 max: 232 x̄: 22.41 x̃: 6
helped stats (rel) min: 0.05% max: 22.60% x̄: 1.30% x̃: 0.41%
HURT stats (abs) min: 1 max: 230 x̄: 24.90 x̃: 10
HURT stats (rel) min: <.01% max: 21.60% x̄: 1.45% x̃: 0.52%
95% mean confidence interval for cycles value: -7.61 -0.36
95% mean confidence interval for cycles %-change: -0.44% -0.02%
Cycles are helped.
No changes on Iron Lake or GM45.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb3e21cd1925c9378b4acb869601bbb011d0de97
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Feb 9 15:21:47 2017 +0000
intel/fs: Use De Morgan's laws to avoid logical-not of a logic result on Gen8+
Instead of emitting ~(a & b), emit (~a | ~b) since logical-not of
operands is free on Gen8+.
v2: Fix swizzles. Fix types for cmod propagation.
v3: Simplify logic for inverting source of inot(ixor(a, b)). Suggested
by Ken.
Skylake and Broadwell had similar results. (Skylake shown)
Skylake
total instructions in shared programs: 15185593 -> 15185583 (<.01%)
instructions in affected programs: 5673 -> 5663 (-0.18%)
helped: 12
HURT: 1
helped stats (abs) min: 1 max: 2 x̄: 1.17 x̃: 1
helped stats (rel) min: 0.30% max: 5.88% x̄: 1.50% x̃: 0.70%
HURT stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
HURT stats (rel) min: 0.12% max: 0.12% x̄: 0.12% x̃: 0.12%
95% mean confidence interval for instructions value: -1.66 0.13
95% mean confidence interval for instructions %-change: -2.60% -0.15%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 370977726 -> 370964249 (<.01%)
cycles in affected programs: 869987 -> 856510 (-1.55%)
helped: 15
HURT: 2
helped stats (abs) min: 2 max: 6640 x̄: 902.20 x̃: 16
helped stats (rel) min: <.01% max: 4.92% x̄: 1.71% x̃: 1.53%
HURT stats (abs) min: 14 max: 42 x̄: 28.00 x̃: 28
HURT stats (rel) min: 1.08% max: 3.18% x̄: 2.13% x̃: 2.13%
95% mean confidence interval for cycles value: -1654.87 69.34
95% mean confidence interval for cycles %-change: -2.29% -0.23%
Inconclusive result (value mean confidence interval includes 0).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8eb36c912955407f9f1d7aba968fe9513cc8e325
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Feb 9 15:20:04 2017 +0000
intel/fs: Emit logical-not of operands on Gen8+
On Gen8+ specifying negation of a logical operation such as AND actually
performs a logical-not. Take advantage of this to generate fewer
instructions.
v2: Major rebase. Use nir_src_as_alu_instr. Fix swizzle handling.
No changes on any pre-Gen8 platform.
Skylake and Broadwell had similar results. (Broadwell shown)
total instructions in shared programs: 15466902 -> 15466274 (<.01%)
instructions in affected programs: 1262953 -> 1262325 (-0.05%)
helped: 682
HURT: 4
helped stats (abs) min: 1 max: 5 x̄: 1.02 x̃: 1
helped stats (rel) min: 0.03% max: 2.40% x̄: 0.18% x̃: 0.04%
HURT stats (abs) min: 1 max: 62 x̄: 17.50 x̃: 3
HURT stats (rel) min: 0.03% max: 1.89% x̄: 0.53% x̃: 0.10%
95% mean confidence interval for instructions value: -1.10 -0.73
95% mean confidence interval for instructions %-change: -0.19% -0.15%
Instructions are helped.
total cycles in shared programs: 410996093 -> 410950440 (-0.01%)
cycles in affected programs: 144389048 -> 144343395 (-0.03%)
helped: 519
HURT: 51
helped stats (abs) min: 1 max: 1060 x̄: 104.46 x̃: 140
helped stats (rel) min: 0.01% max: 10.98% x̄: 0.34% x̃: 0.03%
HURT stats (abs) min: 1 max: 4060 x̄: 167.90 x̃: 22
HURT stats (rel) min: <.01% max: 8.20% x̄: 0.96% x̃: 0.25%
95% mean confidence interval for cycles value: -97.16 -63.02
95% mean confidence interval for cycles %-change: -0.32% -0.13%
Cycles are helped.
total spills in shared programs: 95311 -> 95329 (0.02%)
spills in affected programs: 881 -> 899 (2.04%)
helped: 0
HURT: 4
total fills in shared programs: 93629 -> 93634 (<.01%)
fills in affected programs: 794 -> 799 (0.63%)
helped: 1
HURT: 2
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=06eaaf2de94449f5c5a7cf3dce8894aafa1fb0ae
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Dec 5 11:35:37 2018 -0800
intel/fs: Refactor ALU source and destination handling to a separate function
Other places will need to do this soon to properly handle source
swizzles. The patch looks a little odd, but the change is pretty
straight forward. All of the swizzle and mask handling is moved out,
but the code for handling move instructions and vecN instructions
remains in nir_emit_alu.
I'm not terribly pleased with the "need_dest" parameter, but
get_nir_dest is (somewhat surprisingly) destructive. I am open to
suggestions of alternatives.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb3ca9109cba6d814c2e3843e256b298cfd73661
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Dec 12 18:14:34 2018 -0800
intel/fs: Handle OR source modifiers in algebraic optimization
Found by inspection.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9d5bd050c31b6ca20610a5eadd27068bd5c190b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Jun 19 13:34:57 2018 -0700
intel/fs: Relax type matching rules in cmod propagation from MOV instructions
To allow cmod propagation from a MOV in a sequence like:
and(16) g31<1>UD g20<8,8,1>UD g22<8,8,1>UD
mov.nz.f0(16) null<1>F g31<8,8,1>D
A similar change to the vec4 backend had no effect.
Somewhere between c1ec5820593 and 40fc4b5acd6 (1,094 commits) the
effectiveness of this patch diminished, and as of commit d7e0d47b9de
(nir: Add a bunch of b2[if] optimizations) this optimization no longer
has any effect on any platform.
A later patch "intel/fs: Use De Morgan's laws to avoid logical-not of a
logic result on Gen8+," generates some instruction sequences that
require this change in order for cmod propagation to make progress.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eae19f5f19f57ed669c042fea4f8eb40b8a9e23a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Dec 3 16:30:44 2018 -0800
nir/algebraic: Replace i2b used by bcsel or if-statement with comparison
All of the helped shaders are in Deus Ex. I looked at a couple shaders,
and they have a pattern like:
vec1 32 ssa_373 = i2b32 ssa_345.w
vec1 32 ssa_374 = bcsel ssa_373, ssa_20, ssa_0
...
vec1 32 ssa_377 = ine ssa_345.w, ssa_0
if ssa_377 {
...
vec1 32 ssa_416 = i2b32 ssa_385.w
vec1 32 ssa_417 = bcsel ssa_416, ssa_386, ssa_374
...
}
The massive help occurs because the i2b32 is removed, then other passes
determine that ssa_374 must be ssa_20 inside the if-statement allowing
the first bcsel to also be deleted.
v2: Rebase on 1-bit Boolean changes.
v3: Fix i2b32 vs ine problem in if-statement replacement. Noticed by
Bas.
Skylake
total instructions in shared programs: 15241394 -> 15186287 (-0.36%)
instructions in affected programs: 890583 -> 835476 (-6.19%)
helped: 355
HURT: 0
helped stats (abs) min: 1 max: 497 x̄: 155.23 x̃: 149
helped stats (rel) min: 0.09% max: 16.49% x̄: 6.10% x̃: 6.59%
95% mean confidence interval for instructions value: -165.07 -145.39
95% mean confidence interval for instructions %-change: -6.42% -5.77%
Instructions are helped.
total cycles in shared programs: 373846583 -> 371023357 (-0.76%)
cycles in affected programs: 118972102 -> 116148876 (-2.37%)
helped: 343
HURT: 14
helped stats (abs) min: 45 max: 118284 x̄: 8332.32 x̃: 6089
helped stats (rel) min: 0.03% max: 38.19% x̄: 2.48% x̃: 1.77%
HURT stats (abs) min: 120 max: 4126 x̄: 2482.79 x̃: 3019
HURT stats (rel) min: 0.16% max: 17.37% x̄: 2.13% x̃: 1.11%
95% mean confidence interval for cycles value: -8723.28 -7093.12
95% mean confidence interval for cycles %-change: -2.57% -2.02%
Cycles are helped.
total spills in shared programs: 32401 -> 23465 (-27.58%)
spills in affected programs: 24457 -> 15521 (-36.54%)
helped: 343
HURT: 0
total fills in shared programs: 37866 -> 31765 (-16.11%)
fills in affected programs: 18889 -> 12788 (-32.30%)
helped: 343
HURT: 0
Broadwell and Haswell had similar results. (Haswell shown)
Haswell
total instructions in shared programs: 13764783 -> 13750679 (-0.10%)
instructions in affected programs: 1176256 -> 1162152 (-1.20%)
helped: 334
HURT: 21
helped stats (abs) min: 1 max: 358 x̄: 42.59 x̃: 47
helped stats (rel) min: 0.09% max: 11.81% x̄: 1.30% x̃: 1.37%
HURT stats (abs) min: 1 max: 61 x̄: 5.76 x̃: 1
HURT stats (rel) min: 0.03% max: 1.84% x̄: 0.17% x̃: 0.03%
95% mean confidence interval for instructions value: -43.99 -35.47
95% mean confidence interval for instructions %-change: -1.35% -1.08%
Instructions are helped.
total cycles in shared programs: 386511910 -> 385402528 (-0.29%)
cycles in affected programs: 143831110 -> 142721728 (-0.77%)
helped: 327
HURT: 39
helped stats (abs) min: 16 max: 25219 x̄: 3519.74 x̃: 3570
helped stats (rel) min: <.01% max: 10.26% x̄: 0.95% x̃: 0.96%
HURT stats (abs) min: 16 max: 4881 x̄: 1065.95 x̃: 997
HURT stats (rel) min: <.01% max: 16.67% x̄: 0.70% x̃: 0.24%
95% mean confidence interval for cycles value: -3375.59 -2686.60
95% mean confidence interval for cycles %-change: -0.92% -0.64%
Cycles are helped.
total spills in shared programs: 100480 -> 97846 (-2.62%)
spills in affected programs: 84702 -> 82068 (-3.11%)
helped: 316
HURT: 21
total fills in shared programs: 96877 -> 94369 (-2.59%)
fills in affected programs: 69167 -> 66659 (-3.63%)
helped: 316
HURT: 9
No changes on Ivy Bridge or earlier platforms.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2056ab9936ee67032e1a69bcbf2f1783d67d3c5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Dec 13 15:39:49 2018 -0800
intel/vec4: Emit constants for some ALU sources as immediate values
In some cases of flow control, the constant propagation is not able to
determine that the source of an instruction must be a constant value.
When we still have NIR SSA values, we can easily determine this. Emit
the immediate value during code generation to possible avoid spurious
loads of constants into registers.
I wrote this patch to prevent a couple trivial regressions in vec4
shaders caused by "nir/algebraic: Replace i2b used by bcsel or
if-statement with comparison". The final result was quite a bit better
than that...
No shader-db changes on any Gen8+ platform.
v2: Assert that we never get a negation source modifier on Gen8+.
Suggested by Ken. This should never happen because we don't normally
use vec4 for Gen8+ (requires and environment variable to force it), and
there's no code to generate these negations. Still, erring on the side
of caution is better.
Haswell
total instructions in shared programs: 13776218 -> 13764783 (-0.08%)
instructions in affected programs: 663931 -> 652496 (-1.72%)
helped: 3495
HURT: 1
helped stats (abs) min: 1 max: 30 x̄: 3.28 x̃: 2
helped stats (rel) min: 0.21% max: 10.00% x̄: 1.79% x̃: 1.49%
HURT stats (abs) min: 24 max: 24 x̄: 24.00 x̃: 24
HURT stats (rel) min: 12.24% max: 12.24% x̄: 12.24% x̃: 12.24%
95% mean confidence interval for instructions value: -3.39 -3.15
95% mean confidence interval for instructions %-change: -1.84% -1.75%
Instructions are helped.
total cycles in shared programs: 386818984 -> 386511910 (-0.08%)
cycles in affected programs: 20379636 -> 20072562 (-1.51%)
helped: 3052
HURT: 476
helped stats (abs) min: 2 max: 12516 x̄: 110.40 x̃: 6
helped stats (rel) min: 0.05% max: 24.68% x̄: 1.58% x̃: 0.69%
HURT stats (abs) min: 2 max: 416 x̄: 62.76 x̃: 24
HURT stats (rel) min: 0.10% max: 10.75% x̄: 4.03% x̃: 2.18%
95% mean confidence interval for cycles value: -115.57 -58.51
95% mean confidence interval for cycles %-change: -0.93% -0.73%
Cycles are helped.
total spills in shared programs: 100482 -> 100480 (<.01%)
spills in affected programs: 79 -> 77 (-2.53%)
helped: 3
HURT: 1
total fills in shared programs: 96883 -> 96877 (<.01%)
fills in affected programs: 85 -> 79 (-7.06%)
helped: 4
HURT: 0
Ivy Bridge
total instructions in shared programs: 12000562 -> 11990113 (-0.09%)
instructions in affected programs: 572581 -> 562132 (-1.82%)
helped: 3106
HURT: 0
helped stats (abs) min: 1 max: 30 x̄: 3.36 x̃: 2
helped stats (rel) min: 0.21% max: 10.00% x̄: 1.86% x̃: 1.49%
95% mean confidence interval for instructions value: -3.49 -3.23
95% mean confidence interval for instructions %-change: -1.91% -1.81%
Instructions are helped.
total cycles in shared programs: 180958504 -> 180664500 (-0.16%)
cycles in affected programs: 19991810 -> 19697806 (-1.47%)
helped: 2654
HURT: 486
helped stats (abs) min: 2 max: 12516 x̄: 121.61 x̃: 6
helped stats (rel) min: 0.05% max: 20.66% x̄: 1.48% x̃: 0.68%
HURT stats (abs) min: 2 max: 396 x̄: 59.18 x̃: 24
HURT stats (rel) min: 0.05% max: 9.62% x̄: 3.82% x̃: 2.16%
95% mean confidence interval for cycles value: -125.62 -61.64
95% mean confidence interval for cycles %-change: -0.76% -0.56%
Cycles are helped.
Sandy Bridge
total instructions in shared programs: 10842336 -> 10835438 (-0.06%)
instructions in affected programs: 395340 -> 388442 (-1.74%)
helped: 1926
HURT: 0
helped stats (abs) min: 1 max: 22 x̄: 3.58 x̃: 2
helped stats (rel) min: 0.10% max: 9.68% x̄: 1.78% x̃: 1.42%
95% mean confidence interval for instructions value: -3.73 -3.43
95% mean confidence interval for instructions %-change: -1.84% -1.72%
Instructions are helped.
total cycles in shared programs: 154590074 -> 154569050 (-0.01%)
cycles in affected programs: 8159932 -> 8138908 (-0.26%)
helped: 1670
HURT: 228
helped stats (abs) min: 2 max: 260 x̄: 18.13 x̃: 6
helped stats (rel) min: 0.02% max: 8.70% x̄: 0.74% x̃: 0.28%
HURT stats (abs) min: 2 max: 1798 x̄: 40.58 x̃: 14
HURT stats (rel) min: 0.03% max: 12.97% x̄: 1.04% x̃: 0.31%
95% mean confidence interval for cycles value: -13.51 -8.64
95% mean confidence interval for cycles %-change: -0.60% -0.46%
Cycles are helped.
Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8212357 -> 8206587 (-0.07%)
instructions in affected programs: 323664 -> 317894 (-1.78%)
helped: 1457
HURT: 0
helped stats (abs) min: 1 max: 12 x̄: 3.96 x̃: 3
helped stats (rel) min: 0.33% max: 11.49% x̄: 1.86% x̃: 1.44%
95% mean confidence interval for instructions value: -4.14 -3.78
95% mean confidence interval for instructions %-change: -1.93% -1.78%
Instructions are helped.
total cycles in shared programs: 187668016 -> 187657422 (<.01%)
cycles in affected programs: 14856234 -> 14845640 (-0.07%)
helped: 1372
HURT: 83
helped stats (abs) min: 2 max: 24 x̄: 7.92 x̃: 6
helped stats (rel) min: 0.02% max: 1.14% x̄: 0.12% x̃: 0.08%
HURT stats (abs) min: 2 max: 14 x̄: 3.20 x̃: 2
HURT stats (rel) min: 0.03% max: 0.60% x̄: 0.12% x̃: 0.12%
95% mean confidence interval for cycles value: -7.65 -6.91
95% mean confidence interval for cycles %-change: -0.11% -0.10%
Cycles are helped.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc82ea13508766c5cdd45fc443bac55d72bc2760
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri Mar 1 16:37:31 2019 +0000
Revert "swr/rast: Archrast codegen updates"
This reverts the following commits:
71a76a47ccb34c5c259781ed49b0013e86dfaa31 "swr/codegen: fix autotools build"
7763e664cefd1e394101b37fbc552b50f820f44a "meson/swr: replace hard-coded path with current_build_dir()"
773b3ceacaf6d32135348e07878b8514a4350b0e "swr/rast: Fix autotools and scons codegen"
16e10b8c304481e423e76311f70de5de9e7424b1 "swr/rast: Add general SWTag statistics"
b45a15a39f7630d569fcf1296dac1415eb758249 "swr/rast: Add string handling to AR event framework"
8608a747aafe6aef42fba148bfcdbb3ca136e7de "swr/rast: Add initial SWTag proto definitions"
93cd9905c8fbb98985ae1a61c0eebdb225fd1325 "swr/rast: Cleanup and generalize gen_archrast"
The last one in this list broke all the build systems that can build
this (meson, autotools & scons).
See MR !304 for more details:
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/304
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=12af6b30a34cf7522fc07276ec6b1aa7874b6c74
Author: Fritz Koenig <frkoenig at google.com>
Date: Tue Feb 26 18:31:38 2019 -0800
freedreno/a6xx: Enable UBWC modifier
Adding the supported_modifiers allows buffers
to be created with UBWC
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4715e7a98afbb43872ead144e35272f256549be0
Author: Fritz Koenig <frkoenig at google.com>
Date: Mon Jan 7 12:00:41 2019 -0800
freedreno: UBWC allocator
UBWC requires space for a metadata or flag buffer
that contains compression data. Each 16x4 tile of image
data corresponds to a byte of compression data.
This buffer needs to be stored before (at a lower address)
the image buffer in order to match up with what the
display driver. This allows the display driver to directly
scan-out at UBWC buffer.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e6758a4e774d2906aba31410462346bd00a79cf
Author: Fritz Koenig <frkoenig at google.com>
Date: Mon Jan 7 11:58:53 2019 -0800
freedreno/a6xx: UBWC support
Universal bandwidth compression(UBWC) reduces memory bandwidth
by compressing buffers. This compression takes the form of
a full sized image buffer as well as a smaller metadata buffer.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41082446db4bf728e1722e4bf0ccd34876cd0b04
Author: Fritz Koenig <frkoenig at google.com>
Date: Tue Feb 26 20:06:31 2019 -0800
freedreno: pass count to query_dmabuf_modifiers
query_dmabuf_modifiers needs to know the max number
of modifiers that the list will hold.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2793417ec61ec336b6cb825e06b7eacdd2770204
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 12:02:47 2019 +0000
anv: fix typo
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=258e463db5b8e8df1507dce7012423a5dd1a0260
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 10:43:40 2019 +0000
anv: remove spaces around kwargs assignment
pylint complains:
> C0326: No space allowed around keyword argument assignment
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b704fd2fdf38d4ba50d40e6d95f991ddfd66186
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 10:40:52 2019 +0000
anv: drop unused parameter
I'm guessing a previous version of this script used an index-based map
of entrypoints, but that's not the case anymore.
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b503d4e4583b989e5e2f1bdfca10e4af6d9a2e6c
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 10:40:14 2019 +0000
anv: simplify chained comparison
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1458aa1f78edc22ded5b40f17c148a22fcabfda2
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Mon Feb 25 20:37:59 2019 -0800
nir/copy_prop_vars: handle indirect vector elements
Differently than the direct case, the indirect array derefs of vector
are handled like regular derefs, with the exception that we ignore any
vector entry that has SSA values when performing a load. Such SSA
values don't help loading of the indirect unless we emit an if-ladder.
Copy_derefs are supported for indirects.
Also enable two tests that now pass.
v2: Remove unnecessary temporaries. Be clearer when identifying the
case where copy_entry doesn't help when we are dealing with an
indirect array_deref (of a vector). (Jason)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c0de78cc257240b5e55e033b4df8d7d87dcdfa7
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Tue Jan 29 12:39:28 2019 -0800
nir/copy_prop_vars: prefer using entries from equal derefs
When looking up an entry to use, always prefer an equal match, as it
more likely to contain reusable SSA or derefs to propagate.
This will be necessary when adding entries with array derefs of
vectors, because we don't want the vector if the equal entry (an array
deref of that vector) is present.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=61965afd00af44e5f7c08710e8cd00f4e23b1e7c
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Tue Jan 29 06:35:20 2019 -0800
nir/copy_prop_vars: add tests for indirect array deref
Both on an actual array and on a vector, and an extra test on a vector
mixing direct and indirect access. The vector tests are disabled and
will be enabled by a later commit.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96c32d77763c4b561f751ca360e6539a3c5e7f4d
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Mon Jan 14 15:28:33 2019 -0800
nir/copy_prop_vars: handle load/store of vector elements
When direct array deref is used on a vector type (for loads and
stores), copy_prop_vars is now smart to propagate values it knows
about.
Given a 'vec4 v', storing to v[3] will update the copy entry for v and
it is equivalent to a write to v.w. Loading from v[1] will try first
to see if there's a known value for v.y -- and drop the load in that
case.
The copy entries still always refer to the entire vectors, so the
operations happen on the parent deref (the 'vector') and the values
are fixed accordingly.
It might be the case now that certain entries have not only different
SSA defs in each element but also those come from different components
than they are set to, because stores to individual elements always
come from a SSA definition with a single component.
Tests related to these cases are now enabled.
v2: Instead of asserting on invalid indices, "load" an undef and
remove the store. (Jason)
v3: Merge code path for the cases of is_array_deref_of_vector into the
regular code path. Add a base_index parameter to
value_set_from_value. (code changes by Jason)
v4: Removed the get_entry_for_deref helper, now being used only once.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33dafdc0248cce18ef923313656466dc15ff4c73
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Wed Jan 16 11:48:32 2019 -0800
nir/copy_prop_vars: use NIR_MAX_VEC_COMPONENTS
Also replace uses of 0xf with the appropriate full mask created from
the number of components.
Note that an increase of MAX might make us change how the data is
stored later on, but for now at least we make sure the pass is not
hardcoded.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e84c841fb07cbb3e2d5d28ab55c91ccd8cf41f64
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Wed Jan 16 11:27:43 2019 -0800
nir/copy_prop_vars: rename/refactor store_to_entry helper
The name reflected this function role back when the pass also did dead
write elimination. So rename it to what it does now, which is setting
a value using another value; and narrow the argument list.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c614492517e6af0bc333807dcef12f0939131ba
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Fri Mar 1 08:42:04 2019 +0100
etnaviv: fix compile warnings
Fixes the following compile warnings:
[591/629] Compiling C object 'src/gallium/drivers/etnaviv/df32d18@@etnaviv at sta/etnaviv_context.c.o'.
../../src/ac_mesa/src/gallium/drivers/etnaviv/etnaviv_context.c: In function 'etna_cmd_stream_reset_notify':
../../src/ac_mesa/src/gallium/drivers/etnaviv/etnaviv_context.c:334:22: warning: unused variable 'entry' [-Wunused-variable]
struct set_entry *entry;
^~~~~
[604/629] Compiling C object 'src/gallium/drivers/etnaviv/df32d18@@etnaviv at sta/etnaviv_resource.c.o'.
../../src/ac_mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c: In function 'etna_resource_used':
../../src/ac_mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c:649:22: warning: unused variable 'entry' [-Wunused-variable]
struct set_entry *entry;
^~~~~
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=64813541d575c4244293c6cbcd9739b12a22a76f
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Sat Feb 23 16:15:19 2019 +0100
etnaviv: fix resource usage tracking across different pipe_context's
A pipe_resource can be shared by all the pipe_context's hanging off the
same pipe_screen.
Changes from v2 -> v3:
- add locking with mtx_*() to resource and screen (Marek)
Changes from v3 -> v4:
- drop rsc->lock, just use screen->lock for the entire serialization (Marek)
- simplify etna_resource_used() flush condition, which also prevents
potentially flushing resources twice (Marek)
- don't remove resouces from screen->used_resources in
etna_cmd_stream_reset_notify(), they may still be used in other
contexts and may need flushing there later on (Marek)
Changes from v4 -> v5:
- Fix coding style issues reported by Guido
Changes from v5 -> v6:
- Add missing locking in etna_transfer_map(..) (Boris)
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Signed-off-by: Marek Vasut <marex at denx.de>
Signed-off-by: Boris Brezillon <boris.brezillon at collabora.com>
Tested-by: Marek Vasut <marex at denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon at collabora.com>
Tested-by: Boris Brezillon <boris.brezillon at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1061fa5771496ae95f195c1aa590736cd209414
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Thu Feb 28 07:26:40 2019 +0100
etnaviv: enable ETC2 texture compression support for HALTI0 GPUs
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Reviewed-by: Lucas Stach <l.stach at pengutronix.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d09325c1c9b1f0c22713c78472040428f7e588b
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Thu Feb 28 07:26:39 2019 +0100
etnaviv: hook-up etc2 patching
Changes v1 -> v2:
- Avoid the GPU sampling from the resource that gets mutated by the the
transfer map by setting DRM_ETNA_PREP_WRITE.
Changes v2 -> v3:
- make use of likely(..)
- drop minor optimization regarding rsc->layout == ETNA_LAYOUT_LINEAR
- better documentation why DRM_ETNA_PREP_WRITE is needed
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Reviewed-by: Lucas Stach <l.stach at pengutronix.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8177f623314a025911cc125783c9d63a0cc803e
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Thu Feb 28 07:26:38 2019 +0100
etnaviv: keep track of mapped bo address
Saves us from calling etna_bo_map(..) and saves us from doing the
same offset calcs for map() and unmap() operations.
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Reviewed-by: Lucas Stach <l.stach at pengutronix.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5bb4e6956dcd8e0a6916207cc02af3fe5f631e44
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Thu Feb 28 07:26:37 2019 +0100
etnaviv: implement ETC2 block patching for HALTI0
ETC2 is supported with HALTI0, however that implementation is buggy
in hardware. The blob driver does per-block patching to work around
this. We need to swap colors for t-mode etc2 blocks.
Changes v2 -> v3:
- Drop redundant format check
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Acked-by: Lucas Stach <l.stach at pengutronix.de>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8f863e7189076d7005c4586f1512d0f87afc1d8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Feb 21 10:41:59 2019 -0600
intel/compiler: Re-prefix non-logical surface opcodes with VEC4
The scalar back-end uses SHADER_OPCODE_SEND for all surface messages so
we no longer need the non-logical opcodes there. Prefix them VEC4 so
it's clear that they're only used by the vec4 back-end.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=95ae400abcda4f692fd31c9132462d904f939ec3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Feb 21 10:32:01 2019 -0600
intel/schedule_instructions: Move some comments
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aeaba24fcb98839be73a59f6bb74a39523d79a3d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Feb 21 10:14:17 2019 -0600
intel/compiler: Drop unused surface opcodes
The unused typed surface read/write support in the vec4 back-end has
been dropped and the fs back-end now uses SHADER_OPCODE_SEND for all
image and buffer ops. There's no reason to keep these opcodes around
anymore.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a04c73721591d4b8174f32e5d1fe5db2a5157ea4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Feb 21 09:59:35 2019 -0600
intel/fs: Get rid of the IMAGE_SIZE opcode
Since switching to SHADER_OPCODE_SEND for image operations, we no longer
need the non-logical opcode.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=10b7d14c3177a4631c6b9f3cd850e749793b7e6f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Feb 21 10:12:07 2019 -0600
intel/vec4: Drop dead code for handling typed surface messages
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d437f948201abc56ef8be349012babe37ccfbe4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 11 16:11:35 2019 -0600
intel/fs: Drop the fs_surface_builder
All of the actual abstraction (except possibly setting size_written)
happens as part of the logical opcodes. The only thing that the surface
builder is providing at this point is extra levels of functions to call
through. I'm going to be adding bindless image support soon and all the
extra abstraction here is just getting in the way.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=494a0543e62be59be3a56ca21990eb9eff5ac668
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 11 16:15:50 2019 -0600
intel/fs: Re-order logical surface arguments
It makes more sense to start at the surface then move on to the address
and then the data. Also, this is a really good test of whether or not
we got all the places that use the sources by explicit integer number.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=94f8fd9a0c750e3624bdff3fe7710089bdaa8e6e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 11 14:51:02 2019 -0600
intel/fs: Add an enum type for logical sampler inst sources
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=838c0485e01f3d3403b430aa6df5b4a1f5262dc3
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Feb 28 09:53:28 2019 +0000
scons: Workaround failures with MSVC when using SCons 3.0.[2-4].
This change applies the workaround suggested by Bill Deegan on the
affected SCons versions.
It also adds a comment with the URL explaining why we were using
customizing the decider and max_drift in the first place, as I had
forgotten all about it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109443
Tested-by: liviuprodea at yahoo.com
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=87c2e8cbc9e5e711989c658433aef18620e2c278
Author: Kristian H. Kristensen <hoegsberg at chromium.org>
Date: Mon Feb 25 22:14:53 2019 -0800
freedreno: Fix a couple of warnings
Signed-off-by: Kristian H. Kristensen <hoegsberg at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5a19d1bc8d057845af07b14eb62d83c031fe662
Author: Kristian H. Kristensen <hoegsberg at chromium.org>
Date: Sat Feb 23 11:23:54 2019 -0800
freedreno/a6xx: Don't zero SO buffer addresses
Just disable SO in VPC_SO_BUF_CNTL. Less noise in dumps.
Signed-off-by: Kristian H. Kristensen <hoegsberg at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7dee91610550c00eb2c5e01f1f55474dca9338bd
Author: Kristian H. Kristensen <hoegsberg at chromium.org>
Date: Sat Feb 23 11:12:23 2019 -0800
freedreno/a6xx: Only output MRT control for used framebuffers
Not much of an optimization, but makes for less noise in the command
buffer dumps.
Signed-off-by: Kristian H. Kristensen <hoegsberg at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=df5cd512598ebcea153ba44f36787959e1e367c8
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Wed Feb 27 09:48:46 2019 +0000
gitlab-ci: install xmllint to validate 00-mesa-defaults.conf
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb6b691c574ecc891528947f92be227fb6bcf872
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Tue Feb 26 12:32:04 2019 +0000
driconf: add DTD to allow the drirc xml (00-mesa-defaults.conf) to be validated
This DTD can be used to validate the drirc xml:
$ xmllint --noout --valid 00-mesa-defaults.conf
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c3b2932422a7b8cad6b8373bbcf30328754b76b
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Thu Feb 28 14:48:09 2019 +0000
vulkan: use VkBase{In,Out}Structure instead of a custom struct
VkBaseInStructure and VkBaseOutStructure are part of vulkan_core.h
(which is part of vulkan.h)
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=add4b8930a219008731f76830ffc12b260b7d1da
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Feb 25 17:48:14 2019 +0000
vulkan/overlay: add support for fps output in file
Also make the sampling period configurable.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6b275212dc4eef9014f9e8bd247b72debde4b8b
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Feb 25 12:37:27 2019 +0000
vulkan/overlay: rework option parsing
Makes adding new options easier.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e29a1d36ae72e0192c52efe6865d5b0e58a1358
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Feb 26 12:44:36 2019 +0000
vulkan/overlay: fix min/max computations
This shouldn't be condition to the acquire time being visible.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Acked-by: Eric Engestrom <eric.engestrom at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ad1a05c8314b4b6887f0a23892fa4f7fbca9720
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Tue Feb 19 14:08:08 2019 +0000
egl/sl: use kms_swrast with vgem instead of a random GPU
VGEM and kms_swrast were introduced to work with one another.
All we do is CPU rendering to dumb buffers. There is no reason to carve
out GPU memory, increasing the memory pressure on a device that could
make a better use of it.
Note:
- The original code did not work out of the box, since the dumb buffer
ioctls are not exposed to render nodes.
- This requires libdrm commit 3df8a7f0 ("xf86drm: fallback to MODALIAS
for OF less platform devices")
- The non-kms, swrast is unaffected by this change.
v2:
- elaborate what and how is/isn't working (Eric)
- simplify driver_name handling (Eric)
v3:
- move node_type outside of the loop (Eric)
- kill no longer needed DRM_RENDER_DEV_NAME define
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=218c7b5acaa053482d368afbce4612232731b3a4
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Tue Feb 19 14:08:07 2019 +0000
egl/sl: use drmDevice API to enumerate available devices
This provides for a more comprehensive iteration and slightly more
straight-forward codebase.
v2:
- s/dpy/disp/
- keep original 64 devices (Eric)
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=893421f3159ac6d82bb56b3feccf79dd71eb250e
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Tue Feb 19 14:08:06 2019 +0000
egl/sl: split out swrast probe into separate function
Make the code a bit easier to read.
As a bonus point this makes it obvious that we forgot to call
_eglAddDevice() for the device - do so.
v2:
- s/dpy/disp/ (Eric)
- free(driver_name) on dri2_load_driver_swrast() failure (Eric)
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de> (v1)
Reviewed-by: Gurchetan Singh <gurchetansingh at chromium.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b43b55d4619489e603780adf3c92a36dadcc362b
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date: Wed Feb 27 10:42:00 2019 +0000
nir/spirv: return after emitting a branch in block
When emitting a branch in a block, it does not make sense to continue
processing further instructions, as they will not be reachable.
This fixes a nasty case with a loop with a branch that both then-part
and else-part exits the loop:
%1 = OpLabel
OpLoopMerge %2 %3 None
OpBranchConditional %false %2 %2
%3 = OpLabel
OpBranch %1
%2 = OpLabel
[...]
We know that block %1 will branch always to block %2, which is the merge
block for the loop. And thus a break is emitted. If we keep continuing
processing further instructions, we will be processing the branch
conditional and thus emitting the proper NIR conditional, which leads to
instructions after the break.
This fixes dEQP-VK.graphicsfuzz.continue-and-merge.
CC: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c3287e94d7e5483b31ec9a56447ac5af55d35c1
Author: Eric Engestrom <eric.engestrom at intel.com>
Date: Fri Nov 9 11:55:10 2018 +0000
egl/android: replace magic 0=CbCr,1=CrCb with simple enum
Signed-off-by: Eric Engestrom <eric.engestrom at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a553bedcc1093d899944022739578106eca2f30
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Tue Feb 26 22:29:27 2019 -0800
st/nir: count num_uniforms for FS bultin shader
Usually the uniforms will be assigned locations and have their slots
counted automatically, but for builtin shaders the location assignment
is manual. So count them too otherwise we get num_uniforms == 0.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b344e32cdf7064a1f2ff7ef37027edda6589404f
Author: Ray Zhang <zhanglei002 at gmail.com>
Date: Wed Feb 27 06:54:05 2019 +0000
glx: fix shared memory leak in X11
call XShmDetach to allow X server to free shared memory
Fixes: bcd80be49a8260c2233d "drisw/glx: use XShm if possible"
Signed-off-by: Ray Zhang <zhanglei002 at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e907337fad51ec2f78b202c65a3a25d6b88ffcd8
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Wed Feb 27 14:30:29 2019 +1100
radeonsi/nir: move si_lower_nir() call into compiler thread
This helps improve compile times. For example the shader-db dolphin
shader shaders/dolphin/ubershaders/120.shader_test goes from
~1.69 -> ~1.57 seconds on my machine with this change.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7536af670b7501228628a8c90f9e8456b5aec9e1
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Wed Feb 27 18:26:07 2019 +1100
glsl: fix shader cache for packed param list
Some types of params such as some builtins are always padded. We
need to keep track of this so we can restore the list correctly.
Here we also remove a couple of cache entries that are not actually
required as they get rebuilt by the _mesa_add_parameter() calls.
This patch fixes a bunch of arb_texture_multisample and
arb_sample_shading piglit tests for the radeonsi NIR backend.
Fixes: edded1237607 ("mesa: rework ParameterList to allow packing")
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=07f4b4e4034d6c9f48d136ec39a03e59f65783cb
Author: Yevhenii Kolesnikov <yevhenii.kolesnikov at globallogic.com>
Date: Mon Feb 25 16:21:48 2019 +0200
i965: Fix allow_higher_compat_version workaround limited by OpenGL 3.0
Added check for higher compat profile being allowed
before assigning certain extensions.
Fixes: 272fe9494232 (mesa: enable ARB_texture_buffer_* extensions in the Compatibility profile)
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov at globallogic.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107052
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e184147ddce11e90c269a47af7d7395f5ed9c12
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Wed Feb 27 15:53:21 2019 +0000
intel/compiler: use correct swizzle for replacement
The optimization in 4cd1a0be76883c introduced a replacement of :
cmp(8).z.f0.0 vgrf11.y:D, vgrf10.xxxx:D, vgrf2.xyyy:D
...
cmp(8).nz.f0.0 null.x:D, vgrf11.yyyy:D, 0D
By :
cmp(8).z.f0.0 vgrf15.x:D, vgrf10.xxxx:D, vgrf2.yyyy:D
...
mov(8) vgrf11.y:D, vgrf15.yyyy:D
The first cmp instruction is storing in x while the second mov is
sourcing from y. We need to take into account where the replacement on
the scan_inst destination is going to store thing so that the
replacement mov can source things from the correct location.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 4cd1a0be76883c ("i965/vec4: Propagate conditional modifiers from more compares to other compares")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109759
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
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