Mesa (master): anv,radv,turnip: Lower TG4 offsets with nir_lower_tex

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 08f804ec0c2a4d367787adc4ea7a613170b98e73
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=08f804ec0c2a4d367787adc4ea7a613170b98e73

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Mar 19 13:55:21 2019 -0500

anv,radv,turnip: Lower TG4 offsets with nir_lower_tex

v2: turn on for turnip as well (Karol Herbst)

Reviewed-by: Karol Herbst <kherbst at redhat.com>

---

 src/amd/vulkan/radv_shader.c | 1 +
 src/freedreno/ir3/ir3_nir.c  | 1 +
 src/intel/compiler/brw_nir.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index bd045a0b92f..a1612c829b8 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -313,6 +313,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
 
 	static const nir_lower_tex_options tex_options = {
 	  .lower_txp = ~0,
+	  .lower_tg4_offsets = true,
 	};
 
 	nir_lower_tex(nir, &tex_options);
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 138f8f1af66..606e044d347 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -152,6 +152,7 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 {
 	struct nir_lower_tex_options tex_options = {
 			.lower_rect = 0,
+			.lower_tg4_offsets = true,
 	};
 
 	if (key) {
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 7719ad40251..370b66dc57d 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -683,6 +683,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
       .lower_txb_shadow_clamp = true,
       .lower_txd_shadow_clamp = true,
       .lower_txd_offset_clamp = true,
+      .lower_tg4_offsets = true,
    };
 
    OPT(nir_lower_tex, &tex_options);