Mesa (master): freedreno/ir3: fix sam.s2en encoding

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Module: Mesa
Branch: master
Commit: 1dffb089f903577602bae49931f3d2a71a1a8420
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dffb089f903577602bae49931f3d2a71a1a8420

Author: Rob Clark <robdclark at gmail.com>
Date:   Sat Mar 16 10:29:44 2019 -0400

freedreno/ir3: fix sam.s2en encoding

Signed-off-by: Rob Clark <robdclark at gmail.com>

---

 src/freedreno/ir3/ir3.c | 18 +++++++++---------
 src/freedreno/ir3/ir3.h |  3 +++
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c
index ee13291fb87..9169d2c15f3 100644
--- a/src/freedreno/ir3/ir3.c
+++ b/src/freedreno/ir3/ir3.c
@@ -446,15 +446,17 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
 		struct ir3_info *info)
 {
 	struct ir3_register *dst = instr->regs[0];
-	struct ir3_register *src1 = instr->regs[1];
-	struct ir3_register *src2 = instr->regs[2];
-	struct ir3_register *src3 = instr->regs[3];
+	/* To simplify things when there could be zero, one, or two args other
+	 * than tex/sampler idx, we use the first src reg in the ir to hold
+	 * samp_tex hvec2:
+	 */
+	struct ir3_register *src1 = instr->regs[2];
+	struct ir3_register *src2 = instr->regs[3];
 	instr_cat5_t *cat5 = ptr;
 
 	iassert_type(dst, type_size(instr->cat5.type) == 32)
 
 	assume(src1 || !src2);
-	assume(src2 || !src3);
 
 	if (src1) {
 		cat5->full = ! (src1->flags & IR3_REG_HALF);
@@ -462,17 +464,15 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
 	}
 
 	if (instr->flags & IR3_INSTR_S2EN) {
+		struct ir3_register *samp_tex = instr->regs[1];
 		if (src2) {
 			iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
 			cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
 		}
-		if (src3) {
-			iassert(src3->flags & IR3_REG_HALF);
-			cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF);
-		}
+		iassert(samp_tex->flags & IR3_REG_HALF);
+		cat5->s2en.src3 = reg(samp_tex, info, instr->repeat, IR3_REG_HALF);
 		iassert(!(instr->cat5.samp | instr->cat5.tex));
 	} else {
-		iassert(!src3);
 		if (src2) {
 			iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF));
 			cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF);
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index e38ef9fcb66..4bd7601b8dd 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -1339,6 +1339,9 @@ ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
 	sam = ir3_instr_create(block, opc);
 	sam->flags |= flags;
 	ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
+	// temporary step, extra dummy src which will become the
+	// hvec2(samp, tex) argument:
+	ir3_reg_create(sam, 0, 0);
 	if (src0) {
 		reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
 		reg->wrmask = (1 << (src0->regs_count - 1)) - 1;