Mesa (master): freedreno/ir3: Don't access beyond available regs

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Module: Mesa
Branch: master
Commit: f30d4a1ccaece3578fb92d245cc44a5c7dccdd7d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f30d4a1ccaece3578fb92d245cc44a5c7dccdd7d

Author: Kristian H. Kristensen <hoegsberg at chromium.org>
Date:   Wed Mar 27 23:05:01 2019 -0700

freedreno/ir3: Don't access beyond available regs

emit_cat5() needs to check if the last optional reg is there before it
accesses it.

Signed-off-by: Kristian H. Kristensen <hoegsberg at chromium.org>
Reviewed-by: Rob Clark <robdclark at gmail.com>

---

 src/freedreno/ir3/ir3.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c
index f209585dd9a..1bded7dd122 100644
--- a/src/freedreno/ir3/ir3.c
+++ b/src/freedreno/ir3/ir3.c
@@ -451,10 +451,13 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
 	 * than tex/sampler idx, we use the first src reg in the ir to hold
 	 * samp_tex hvec2:
 	 */
-	struct ir3_register *src1 = instr->regs[2];
-	struct ir3_register *src2 = instr->regs[3];
+	struct ir3_register *src1;
+	struct ir3_register *src2;
 	instr_cat5_t *cat5 = ptr;
 
+	iassert((instr->regs_count == 2) ||
+			(instr->regs_count == 3) || (instr->regs_count == 4));
+
 	switch (instr->opc) {
 	case OPC_DSX:
 	case OPC_DSXPP_1:
@@ -462,11 +465,11 @@ static int emit_cat5(struct ir3_instruction *instr, void *ptr,
 	case OPC_DSYPP_1:
 		iassert((instr->flags & IR3_INSTR_S2EN) == 0);
 		src1 = instr->regs[1];
-		src2 = instr->regs[2];
+		src2 = instr->regs_count > 2 ? instr->regs[2] : NULL;
 		break;
 	default:
 		src1 = instr->regs[2];
-		src2 = instr->regs[3];
+		src2 = instr->regs_count > 3 ? instr->regs[3] : NULL;
 		break;
 	}