Mesa (master): iris/icl: Set Enabled Texel Offset Precision Fix bit

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Thu Mar 28 20:10:21 UTC 2019


Module: Mesa
Branch: master
Commit: e0f4359ec12e8e8dcd96d658b8ef3e308ffe8859
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0f4359ec12e8e8dcd96d658b8ef3e308ffe8859

Author: Anuj Phogat <anuj.phogat at gmail.com>
Date:   Tue Mar 26 15:45:29 2019 -0700

iris/icl: Set Enabled Texel Offset Precision Fix bit

h/w specification requires this bit to be always set.
See Mesa commit 5eb173304bd.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/gallium/drivers/iris/iris_state.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 1ae9c557a27..ddce0023dbe 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -707,6 +707,13 @@ iris_init_render_context(struct iris_screen *screen,
       }
       iris_emit_lri(batch, SAMPLER_MODE, reg_val);
 
+      /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
+      iris_pack_state(GENX(HALF_SLICE_CHICKEN7), &reg_val, reg) {
+         reg.EnabledTexelOffsetPrecisionFix = 1;
+         reg.EnabledTexelOffsetPrecisionFixMask = 1;
+      }
+      iris_emit_lri(batch, HALF_SLICE_CHICKEN7, reg_val);
+
       // XXX: 3D_MODE?
 #endif
 




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