Mesa (master): 34 new commits
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Fri Nov 8 01:02:17 UTC 2019
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a4fad7f40f13b47ff09d0f1dd43459ea18a327e
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Thu Nov 7 16:44:33 2019 -0800
freedreno/ir3: Use regid() helper when setting up precolor regs
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3699a74a4323a8e0873a1be3e2f788786b813bf7
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:51:38 2019 -0700
freedreno/a6xx: Turn on tessellation shaders
Wow. Very triangle. So shader.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53782571ae3b7c3f112c01914937ee622b6690c5
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 29 16:26:34 2019 -0700
freedreno/a6xx: Only use merged regs and four quads for VS+FS
When other geometry stages are present, we chose two quads and no
merged regs.
Acked-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=07aedc367cbfe5358da4b274483a525e7cfaf04c
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 16:26:11 2019 -0700
freedreno/blitter: Save tessellation state
We have tessellation state now.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2d0c8186d1c3fe929147950cc887a5c5d7978dd
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Thu Nov 7 16:32:24 2019 -0800
freedreno/a6xx: Only set emit.hs/ds when we're drawing patches
At least the gallium blitter helper will call us to draw with
tessellation shaders set but a non-patch primitive.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e58479088548a547e4a5df59797adf1f8003feca
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:49:47 2019 -0700
freedreno: Use bypass rendering for tessellation
It seems like tiling could work in the Adreno architecture, but we've
only ever seen bypass rendering with tessellation. For now, let's do
that too.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=47e2c195115854452a5560c59f82bebfc989694a
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 20:03:07 2019 -0700
freedreno/a6xx: Program state for tessellation stages
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03a30e7c3d6cd6737ce60e35b23eec5e7b1a46ba
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:58:59 2019 -0700
freedreno/a6xx: Emit constant parameters for tessellation stages
Assemble the information the stages need and emit the constants.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5dd51d2da75fdbabaa9cef1c9b4bf976117691b5
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 20:05:47 2019 -0700
freedreno/a6xx: Allocate and program tessellation buffer
Tessellation needs a couple of buffers that should hold the entire
output from a full VS+TCS draw call.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0ef3e96970e0b8388c9d7be678b70217b3a8506
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:47:50 2019 -0700
freedreno/a6xx: Build the right draw command for tessellation
We need to select the right primitive type, set a bit to turn on
tessellation and or in the TES output primitive type.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7272e8a70965d679d4545dffbc8099d99431f80b
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:44:42 2019 -0700
freedreno/ir3: Allocate const space for tessellation parameters
The tessellation stages need size and stride or the patch layout as
well as locations of attributes in the patch. The tesselation stages
also use two system memory BOs and need the iovas of those.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8739ea3ab5db36e0ca1bcba63616f86ba7cf881e
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:39:47 2019 -0700
freedreno/ir3: Pre-color TCS header and primitive ID inputs
Similar to GS, the registers are shared and not reinitialized betewen
VS and TCS, so we need to make sure to allocate the same registers for
the system values between stages.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b12ebe3e8133f7d698a74d80a5b4f486089f5fda
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 20:21:13 2019 -0700
freedreno/ir3: Don't assume binning shader is always VS
In tessellation mode, the TES is (probably) the binning shader.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cedeba7c9cc41b798eda14bd28f32f35490d1ab
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:37:53 2019 -0700
freedreno/ir3: Setup inputs and outputs for tessellation stages
Similar to GS, some inputs are reused when the chsh from VS to TCS or
TES to GS, so we need to make sure we setup the right inputs and make
the shared system values outputs so they don't get clobbered.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e28fbbd86120955360f814520500ac292c1f32df
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:30:51 2019 -0700
freedreno/ir3: Implement TCS synchronization intrinsics
We add two new IR3 specific nir intrinsics that map to the new condend
and endpatch instructions.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4915231b8a786466041f34dd3e83f31470d40dde
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:29:07 2019 -0700
freedreno/ir3: Implement tess coord intrinsic
Our lowering pass made the z component unused by replacing its uses
by 1 - x - y. The intrinsic implementation then just need to return
the x and y components.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e16e48d00c84588c6ef5fcb87e375a1afd6fef74
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 19:26:30 2019 -0700
freedreno/ir3: End TES with chsh when using GS
When we have both TES and GS, the TES needs to chain to the VS with
chmask and chsh GS just like the VS does to either TCS or GS.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=581cd596928bf6bc34ef806e4f015a86ab82f728
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 18:19:50 2019 -0700
freedreno/ir3: Add new synchronization opcodes
There are two new opcodes in use in tesselation control shaders:
category 0, opcodes 13 and 15. unk13 is a kill type of instruction
that terminates threads where !p0.x and it used to narrow down a patch
wavefront to just thread 0. Then, once thread 0 has written the tess
levels, it issues unk15, which might signal the TE that another patch
has been fully written.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=56ed835bffb0e9cd6770a788b6605b84bd54683c
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 17:30:48 2019 -0700
freedreno/ir3: Extend geometry lowering pass to handle tessellation
VS and TCS pass varyings the same way as VS and GS does. TCS then
writes entire patch to a system memory BO and TES eventually reads
back from the BO once the TE starts generating vertices. TES outputs
vertices the same way as VS and GS, except when there's a GS as well,
in which case TES passes varyings to GS same way the VS would.
In addition, the TCS needs a little bit of control flow massaging so
that it only runs for valid invocations needs a couple of unknown
instructions to synchronize with the TE.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8621fbc37b205b142639a582cf6a2a76d68b25cb
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 17:16:09 2019 -0700
freedreno/ir3: Add tessellation field to shader key
Whether we're tessellating and which primitives the TES outputs
affects the entire pipeline so let's add a field to the key to track
that.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=77b96b843e4d58a1462976dacf6ae314de815881
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 16:37:35 2019 -0700
freedreno/ir3: Use imul24 in offset calculations
With the imul24 opcode in place, we can now use it for computing local
offsets (ie for ldlw/stlw).
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41984c84227a37b6836a57a39348c70b49457212
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 16:33:18 2019 -0700
freedreno/ir3: Add ir3 intrinsics for tessellation
These provide the iovas for system memory buffers used for
tessellation as well as a new HW specific system value.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6209a50bb13a40c0823f4c53eb1566328ba6630
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 16:24:26 2019 -0700
freedreno: Don't count primitives for patches
The gallium helper doesn't like patches and we can't determine how
many primitives it gets tessellated into anyway. On gens where we
have tessellation, we get the prim count from a HW counter so just
skip counting on the CPU.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe450ef4cf672f4f66ea1966cc96bc706b864357
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 16:16:35 2019 -0700
freedreno/ir3: Add load and store intrinsics for global io
These intrinsics take a ivec2 for the 64 bit base address and a
integer offset.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d67da13a3f9e22bc5490e2e658f46806125fce1
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 16:07:45 2019 -0700
freedreno/ir3: Emit link map as byte or dwords offsets as needed
Stages that load inputs with ldlw (TCS, GS) need byte offsets, stages
that load with ldg (TES) need dwords offsets.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f3b52ce503597ccb170b7caae3b3f19890dce46
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 22 16:03:36 2019 -0700
freedreno/a6xx: Add register offset for STG/LDG
These instructions take a 64 bit iova as two conescutive registers and
a immediate offset. This patch adds support for the offset to be a
single register, which is added to the 64 bit iova.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d16ec4a717266bb702b718ec05e083b83eb5490
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Thu Oct 31 14:43:58 2019 -0700
freedreno/a6x: Rename z/s formats
What we call eRB6_Z24_UNORM_S8_UINT now is actually
RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 and RB6_X8Z24_UNORM is actually
RB6_Z24_UNORM_S8_UINT.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=50124afe3408108dc742c81dca3c071194ed678d
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Fri Nov 1 15:16:44 2019 -0700
freedreno/a6xx: Fix layered texture type enum
2D array textures and 3D textures are different enum values after all.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0276d0766d4b62d28097d74a049808b1e10c1f9b
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Thu Oct 31 14:21:32 2019 -0700
freedreno: Add nogmem debug option to force bypass rendering
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7fed7c2a7d2fcb3fbb490ad5fbc2db270c33a1f1
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Thu Sep 19 17:13:34 2019 -0700
freedreno/a6xx: Clear sysmem with CP_BLIT
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0b443dcab09a913e5fc2ea5a61d89e6ccbd4c35
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Wed Oct 30 17:18:48 2019 -0700
freedreno/a6xx: Fix primitive counters again
We use one mechanism for (REG_A6XX_RBBM_PRIMCTR_8_LO)
PIPE_QUERY_PRIMITIVES_GENERATED, which counts all primitives that exit
the geometry pipeline, whether or not xfb is on. Then for
PIPE_QUERY_PRIMITIVES_EMITTED, we use the CP_EVENT_WRITE subfunction
that writes out per-stream counts for generated and emitted, but only
when xfb is enabled.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=835f8d1ba199fd99bdd9157a978bcf43b017ede1
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Thu Oct 31 10:01:00 2019 -0700
freedreno/registers: Add comments about primitive counters
Adding comments about best guess at what the counters count.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96968d0ba2ec917920993e699f420291d829fac2
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Thu Oct 31 10:02:12 2019 -0700
freedreno/registers: Move SP_PRIMITIVE_CNTL and SP_VS_VPC_DST
Move these two to be in order with the other VS regs.
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba54f7dd038997015867604d2aeffa172f694205
Author: Kristian H. Kristensen <hoegsberg at google.com>
Date: Tue Oct 29 12:19:28 2019 -0700
freedreno/registers: Fix typo
Signed-off-by: Kristian H. Kristensen <hoegsberg at google.com>
Acked-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Rob Clark <robdclark at gmail.com>
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