Mesa (master): intel/compiler: fix nir_op_{i,u}*32 on ICL

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Module: Mesa
Branch: master
Commit: eb6352162dde1445f1fe7a408e79f4ecfdf3703c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb6352162dde1445f1fe7a408e79f4ecfdf3703c

Author: Paulo Zanoni <paulo.r.zanoni at intel.com>
Date:   Mon Nov 11 16:49:15 2019 -0800

intel/compiler: fix nir_op_{i,u}*32 on ICL

On ICL we have the src1 restriction which is applied through
fix_byte_src() and potentially changes the type of the operands from 8
to 32 bits. When this change happens, we fall into the "else if
(bit_size < 32)" case and miscompute src_type because it takes into
consideration bit_size (8) instead of the adjusted size of temp_op
(32). This results in the shader reading unused memory, giving us
mostly failures, but occasional passes due to whatever was already in
the registers we were reading.

This commit fixes a lot of dEQP subgroup i8vec2 tests on ICL, such as:
    dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2

This can also be verified by simply changing fix_byte_src() to apply
on all platforms.

Fixes: 5847de6e9afe ("intel/compiler: don't use byte operands for src1 on ICL")
Reviewed-by: Ivan Briano <ivan.briano at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

---

 src/intel/compiler/brw_fs_nir.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index d767b123036..1447a7b61e5 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1401,7 +1401,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
       temp_op[0] = bld.fix_byte_src(op[0]);
       temp_op[1] = bld.fix_byte_src(op[1]);
 
-      const uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
+      const uint32_t bit_size = type_sz(temp_op[0].type) * 8;
       if (bit_size != 32)
          dest = bld.vgrf(temp_op[0].type, 1);