Mesa (master): pan/midgard: Fix vertex texturing on early Midgard

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 29f5b00e6e3def63682ac3cf46ff15dc51509d61
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=29f5b00e6e3def63682ac3cf46ff15dc51509d61

Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Nov 11 08:15:46 2019 -0500

pan/midgard: Fix vertex texturing on early Midgard

We use a different set of texture registers, probably to save hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Tested-by: Andre Heider <a.heider at gmail.com>

---

 src/panfrost/midgard/midgard_ra.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index 7035a2a160b..85ad96ff312 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -441,6 +441,16 @@ allocate_registers(compiler_context *ctx, bool *spilled)
 
         lcra_set_disjoint_class(l, REG_CLASS_TEXR, REG_CLASS_TEXW);
 
+        /* To save space on T720, we don't have real texture registers.
+         * Instead, tex inputs reuse the load/store pipeline registers, and
+         * tex outputs use work r0/r1. Note we still use TEXR/TEXW classes,
+         * noting that this handles interferences and sizes correctly. */
+
+        if (ctx->gpu_id == 0x0720) {
+                l->class_start[REG_CLASS_TEXR] = l->class_start[REG_CLASS_LDST];
+                l->class_start[REG_CLASS_TEXW] = l->class_start[REG_CLASS_WORK];
+        }
+
         unsigned *found_class = calloc(sizeof(unsigned), ctx->temp_count);
 
         mir_foreach_instr_global(ctx, ins) {