Mesa (master): 22 new commits

Sat Nov 23 05:05:53 UTC 2019

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad40715f3595537cfcc3d489f86d6c4dd7f34cc6
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Nov 21 20:24:08 2019 -0500

    nir/serialize: support any num_components for remaining instructions
    
    Only NPOT vectors greater than vec4 use the extra uint32.
    
    This is for instructions that share the dest code.
    load_const and undef already support 1-16 in the header.
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c028449c011c395ed64eb2d873c0efb4deb2c6e8
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Nov 21 20:23:27 2019 -0500

    nir/serialize: use 3 unused bits in intrinsic for packed_const_indices
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d44aed09ee69c712e91ce4f8af2758ff87fb0b0
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Nov 21 19:45:46 2019 -0500

    nir/serialize: don't serialize redundant nir_intrinsic_instr::num_components
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2df670b1419296060d6914eb9a930171a38092c
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 11 22:33:49 2019 -0500

    nir/serialize: serialize writemask for vec8 and vec16
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5c5388234a4d3ec8e05d15f1b9663b19342cdf5
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 11 22:28:17 2019 -0500

    nir/serialize: serialize swizzles for vec8 and vec16
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1a48d54ea8989c3eb0a86510f68f707de523a72
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Nov 7 00:28:01 2019 -0500

    nir/serialize: reuse the writemask field for 2 src X swizzles of SSA ALU
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=487a495cc09e15ab1582309ffee0fbeb302d5f45
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Nov 5 22:14:28 2019 -0500

    nir/serialize: remove up to 3 consecutive equal ALU instruction headers
    
    vec4 scalarized ALUs typically have 4 equal instruction headers, so remove
    the last 3.
    
    There are no bits left in the ALU header for more flags, so future
    extensions of NIR will have to use something like instr_type == 15
    to describe more complex ALU instructions.
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3fa9de2a98b342b8023bfda0f172a065dbd575b
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Nov 5 18:10:40 2019 -0500

    nir/serialize: try to pack both deref array src into 32 bits
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed6b01d5e034faae08bbed0198a780e18bd0a1d9
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Nov 5 18:24:27 2019 -0500

    nir/serialize: cleanup - fold nir_deref_type_var cases into switches
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0cd67d29203755cec7017a6894704d2a55bee06
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Nov 5 17:53:32 2019 -0500

    nir/serialize: try to put deref->var index into the unused bits of the header
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca201bfe7060638cfd39a8d263df93cb0c39c75b
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Nov 5 17:39:38 2019 -0500

    nir/serialize: don't serialize mode for deref non-cast instructions
    
    It can be derived from src and var. This frees 10 bits in the header
    that will be used later.
    
    "mode" is moved in the structure, because those bits will be used for
    something else later.
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2286340fde63d7dfbb4f70a6ffa254989c1477b1
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 4 20:11:11 2019 -0500

    nir/serialize: don't store deref types if not needed
    
    - type_cast: deduplicate types if the last one is the same
    - derive the type from the parent for other derefs
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=70a7f85149db1578430fb934c8b4e84065a9f74b
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Nov 5 00:09:29 2019 -0500

    nir/serialize: try to pack two alu srcs into 1 uint32
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef4630cf4f3ec2561d437909e2681869fee14873
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 4 23:29:33 2019 -0500

    nir/serialize: pack nir_intrinsic_instr::const_index[] better
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3346b275a476a5d3144b732610baa6b895a680a
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 4 22:25:15 2019 -0500

    nir/serialize: pack 1-component constants into 20 bits if possible
    
    The majority of constants can be packed like this.
    
    v2: - use enum for the packing encoding,
        - trim packed_value to 20 bits add 1 bit to last_component,
          which simplifies a later commit
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=75f7c388637917d796fdf86c645a03c31621c1ca
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 4 22:15:17 2019 -0500

    nir/serialize: pack load_const with non-64-bit constants better
    
    v2: use blob_write_uint8/16
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net> (v1)
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a572ba673b16e10576b45f9dd84638c0a22ce166
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 4 21:31:40 2019 -0500

    nir/serialize: try to store a diff in var data locations instead of var data
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8314678ee95b8eff211cbdd2086e3197a7ef696
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 4 20:11:11 2019 -0500

    nir/serialize: deduplicate serialized var types by reusing the last unique one
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=545415f45f35642047154cfda515896f9b5c0448
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Nov 4 19:42:42 2019 -0500

    nir/serialize: don't serialize var->data for temporaries
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c358c2b2bfbf6f68f1e181c980bbb17335f9a267
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed Oct 30 18:14:37 2019 -0400

    nir/serialize: pack src better and limit the object count to 1M from 1G
    
    We need to limit the object count to 1M to free 10 bits for the src
    modifiers.
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=35655865cbde648f6dcfad38fa095d9ec0c4e45b
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Oct 25 02:39:54 2019 -0400

    nir/serialize: pack instructions better
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fe1d7822b07bf78975c12a2e27db6e5817b1a6b
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Nov 19 19:36:36 2019 -0500

    util/blob: add 8-bit and 16-bit reads and writes
    
    Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>