Mesa (master): freedreno/registers: add missing MH perfcounter enum for a2xx
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gitlab-mirror at kemper.freedesktop.org
Wed Nov 27 17:15:09 UTC 2019
Module: Mesa
Branch: master
Commit: 0d0c8a9e82930ad368ad17c23b1df630e7346ac9
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d0c8a9e82930ad368ad17c23b1df630e7346ac9
Author: Jonathan Marek <jonathan at marek.ca>
Date: Wed Nov 27 10:38:14 2019 -0500
freedreno/registers: add missing MH perfcounter enum for a2xx
Signed-off-by: Jonathan Marek <jonathan at marek.ca>
Reviewed-by: Rob Clark <robdclark at chromium.org>
---
src/freedreno/registers/a2xx.xml | 185 +++++++++++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
diff --git a/src/freedreno/registers/a2xx.xml b/src/freedreno/registers/a2xx.xml
index e486f804bc7..9b6bf752ab4 100644
--- a/src/freedreno/registers/a2xx.xml
+++ b/src/freedreno/registers/a2xx.xml
@@ -834,6 +834,191 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/>
</enum>
+<enum name="a2xx_mh_perfcnt_select">
+ <value value="0" name="CP_R0_REQUESTS"/>
+ <value value="1" name="CP_R1_REQUESTS"/>
+ <value value="2" name="CP_R2_REQUESTS"/>
+ <value value="3" name="CP_R3_REQUESTS"/>
+ <value value="4" name="CP_R4_REQUESTS"/>
+ <value value="5" name="CP_TOTAL_READ_REQUESTS"/>
+ <value value="6" name="CP_TOTAL_WRITE_REQUESTS"/>
+ <value value="7" name="CP_TOTAL_REQUESTS"/>
+ <value value="8" name="CP_DATA_BYTES_WRITTEN"/>
+ <value value="9" name="CP_WRITE_CLEAN_RESPONSES"/>
+ <value value="10" name="CP_R0_READ_BURSTS_RECEIVED"/>
+ <value value="11" name="CP_R1_READ_BURSTS_RECEIVED"/>
+ <value value="12" name="CP_R2_READ_BURSTS_RECEIVED"/>
+ <value value="13" name="CP_R3_READ_BURSTS_RECEIVED"/>
+ <value value="14" name="CP_R4_READ_BURSTS_RECEIVED"/>
+ <value value="15" name="CP_TOTAL_READ_BURSTS_RECEIVED"/>
+ <value value="16" name="CP_R0_DATA_BEATS_READ"/>
+ <value value="17" name="CP_R1_DATA_BEATS_READ"/>
+ <value value="18" name="CP_R2_DATA_BEATS_READ"/>
+ <value value="19" name="CP_R3_DATA_BEATS_READ"/>
+ <value value="20" name="CP_R4_DATA_BEATS_READ"/>
+ <value value="21" name="CP_TOTAL_DATA_BEATS_READ"/>
+ <value value="22" name="VGT_R0_REQUESTS"/>
+ <value value="23" name="VGT_R1_REQUESTS"/>
+ <value value="24" name="VGT_TOTAL_REQUESTS"/>
+ <value value="25" name="VGT_R0_READ_BURSTS_RECEIVED"/>
+ <value value="26" name="VGT_R1_READ_BURSTS_RECEIVED"/>
+ <value value="27" name="VGT_TOTAL_READ_BURSTS_RECEIVED"/>
+ <value value="28" name="VGT_R0_DATA_BEATS_READ"/>
+ <value value="29" name="VGT_R1_DATA_BEATS_READ"/>
+ <value value="30" name="VGT_TOTAL_DATA_BEATS_READ"/>
+ <value value="31" name="TC_TOTAL_REQUESTS"/>
+ <value value="32" name="TC_ROQ_REQUESTS"/>
+ <value value="33" name="TC_INFO_SENT"/>
+ <value value="34" name="TC_READ_BURSTS_RECEIVED"/>
+ <value value="35" name="TC_DATA_BEATS_READ"/>
+ <value value="36" name="TCD_BURSTS_READ"/>
+ <value value="37" name="RB_REQUESTS"/>
+ <value value="38" name="RB_DATA_BYTES_WRITTEN"/>
+ <value value="39" name="RB_WRITE_CLEAN_RESPONSES"/>
+ <value value="40" name="AXI_READ_REQUESTS_ID_0"/>
+ <value value="41" name="AXI_READ_REQUESTS_ID_1"/>
+ <value value="42" name="AXI_READ_REQUESTS_ID_2"/>
+ <value value="43" name="AXI_READ_REQUESTS_ID_3"/>
+ <value value="44" name="AXI_READ_REQUESTS_ID_4"/>
+ <value value="45" name="AXI_READ_REQUESTS_ID_5"/>
+ <value value="46" name="AXI_READ_REQUESTS_ID_6"/>
+ <value value="47" name="AXI_READ_REQUESTS_ID_7"/>
+ <value value="48" name="AXI_TOTAL_READ_REQUESTS"/>
+ <value value="49" name="AXI_WRITE_REQUESTS_ID_0"/>
+ <value value="50" name="AXI_WRITE_REQUESTS_ID_1"/>
+ <value value="51" name="AXI_WRITE_REQUESTS_ID_2"/>
+ <value value="52" name="AXI_WRITE_REQUESTS_ID_3"/>
+ <value value="53" name="AXI_WRITE_REQUESTS_ID_4"/>
+ <value value="54" name="AXI_WRITE_REQUESTS_ID_5"/>
+ <value value="55" name="AXI_WRITE_REQUESTS_ID_6"/>
+ <value value="56" name="AXI_WRITE_REQUESTS_ID_7"/>
+ <value value="57" name="AXI_TOTAL_WRITE_REQUESTS"/>
+ <value value="58" name="AXI_TOTAL_REQUESTS_ID_0"/>
+ <value value="59" name="AXI_TOTAL_REQUESTS_ID_1"/>
+ <value value="60" name="AXI_TOTAL_REQUESTS_ID_2"/>
+ <value value="61" name="AXI_TOTAL_REQUESTS_ID_3"/>
+ <value value="62" name="AXI_TOTAL_REQUESTS_ID_4"/>
+ <value value="63" name="AXI_TOTAL_REQUESTS_ID_5"/>
+ <value value="64" name="AXI_TOTAL_REQUESTS_ID_6"/>
+ <value value="65" name="AXI_TOTAL_REQUESTS_ID_7"/>
+ <value value="66" name="AXI_TOTAL_REQUESTS"/>
+ <value value="67" name="AXI_READ_CHANNEL_BURSTS_ID_0"/>
+ <value value="68" name="AXI_READ_CHANNEL_BURSTS_ID_1"/>
+ <value value="69" name="AXI_READ_CHANNEL_BURSTS_ID_2"/>
+ <value value="70" name="AXI_READ_CHANNEL_BURSTS_ID_3"/>
+ <value value="71" name="AXI_READ_CHANNEL_BURSTS_ID_4"/>
+ <value value="72" name="AXI_READ_CHANNEL_BURSTS_ID_5"/>
+ <value value="73" name="AXI_READ_CHANNEL_BURSTS_ID_6"/>
+ <value value="74" name="AXI_READ_CHANNEL_BURSTS_ID_7"/>
+ <value value="75" name="AXI_READ_CHANNEL_TOTAL_BURSTS"/>
+ <value value="76" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0"/>
+ <value value="77" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1"/>
+ <value value="78" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2"/>
+ <value value="79" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3"/>
+ <value value="80" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4"/>
+ <value value="81" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5"/>
+ <value value="82" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6"/>
+ <value value="83" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7"/>
+ <value value="84" name="AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ"/>
+ <value value="85" name="AXI_WRITE_CHANNEL_BURSTS_ID_0"/>
+ <value value="86" name="AXI_WRITE_CHANNEL_BURSTS_ID_1"/>
+ <value value="87" name="AXI_WRITE_CHANNEL_BURSTS_ID_2"/>
+ <value value="88" name="AXI_WRITE_CHANNEL_BURSTS_ID_3"/>
+ <value value="89" name="AXI_WRITE_CHANNEL_BURSTS_ID_4"/>
+ <value value="90" name="AXI_WRITE_CHANNEL_BURSTS_ID_5"/>
+ <value value="91" name="AXI_WRITE_CHANNEL_BURSTS_ID_6"/>
+ <value value="92" name="AXI_WRITE_CHANNEL_BURSTS_ID_7"/>
+ <value value="93" name="AXI_WRITE_CHANNEL_TOTAL_BURSTS"/>
+ <value value="94" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0"/>
+ <value value="95" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1"/>
+ <value value="96" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2"/>
+ <value value="97" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3"/>
+ <value value="98" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4"/>
+ <value value="99" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5"/>
+ <value value="100" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6"/>
+ <value value="101" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7"/>
+ <value value="102" name="AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN"/>
+ <value value="103" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0"/>
+ <value value="104" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1"/>
+ <value value="105" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2"/>
+ <value value="106" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3"/>
+ <value value="107" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4"/>
+ <value value="108" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5"/>
+ <value value="109" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6"/>
+ <value value="110" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7"/>
+ <value value="111" name="AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES"/>
+ <value value="112" name="TOTAL_MMU_MISSES"/>
+ <value value="113" name="MMU_READ_MISSES"/>
+ <value value="114" name="MMU_WRITE_MISSES"/>
+ <value value="115" name="TOTAL_MMU_HITS"/>
+ <value value="116" name="MMU_READ_HITS"/>
+ <value value="117" name="MMU_WRITE_HITS"/>
+ <value value="118" name="SPLIT_MODE_TC_HITS"/>
+ <value value="119" name="SPLIT_MODE_TC_MISSES"/>
+ <value value="120" name="SPLIT_MODE_NON_TC_HITS"/>
+ <value value="121" name="SPLIT_MODE_NON_TC_MISSES"/>
+ <value value="122" name="STALL_AWAITING_TLB_MISS_FETCH"/>
+ <value value="123" name="MMU_TLB_MISS_READ_BURSTS_RECEIVED"/>
+ <value value="124" name="MMU_TLB_MISS_DATA_BEATS_READ"/>
+ <value value="125" name="CP_CYCLES_HELD_OFF"/>
+ <value value="126" name="VGT_CYCLES_HELD_OFF"/>
+ <value value="127" name="TC_CYCLES_HELD_OFF"/>
+ <value value="128" name="TC_ROQ_CYCLES_HELD_OFF"/>
+ <value value="129" name="TC_CYCLES_HELD_OFF_TCD_FULL"/>
+ <value value="130" name="RB_CYCLES_HELD_OFF"/>
+ <value value="131" name="TOTAL_CYCLES_ANY_CLNT_HELD_OFF"/>
+ <value value="132" name="TLB_MISS_CYCLES_HELD_OFF"/>
+ <value value="133" name="AXI_READ_REQUEST_HELD_OFF"/>
+ <value value="134" name="AXI_WRITE_REQUEST_HELD_OFF"/>
+ <value value="135" name="AXI_REQUEST_HELD_OFF"/>
+ <value value="136" name="AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT"/>
+ <value value="137" name="AXI_WRITE_DATA_HELD_OFF"/>
+ <value value="138" name="CP_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="139" name="VGT_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="140" name="TC_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="141" name="TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="142" name="RB_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="143" name="TOTAL_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="144" name="CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
+ <value value="145" name="VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
+ <value value="146" name="TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
+ <value value="147" name="RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
+ <value value="148" name="TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT"/>
+ <value value="149" name="TOTAL_MH_READ_REQUESTS"/>
+ <value value="150" name="TOTAL_MH_WRITE_REQUESTS"/>
+ <value value="151" name="TOTAL_MH_REQUESTS"/>
+ <value value="152" name="MH_BUSY"/>
+ <value value="153" name="CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
+ <value value="154" name="VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
+ <value value="155" name="TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
+ <value value="156" name="RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
+ <value value="157" name="TC_ROQ_N_VALID_ENTRIES"/>
+ <value value="158" name="ARQ_N_ENTRIES"/>
+ <value value="159" name="WDB_N_ENTRIES"/>
+ <value value="160" name="MH_READ_LATENCY_OUTST_REQ_SUM"/>
+ <value value="161" name="MC_READ_LATENCY_OUTST_REQ_SUM"/>
+ <value value="162" name="MC_TOTAL_READ_REQUESTS"/>
+ <value value="163" name="ELAPSED_CYCLES_MH_GATED_CLK"/>
+ <value value="164" name="ELAPSED_CLK_CYCLES"/>
+ <value value="165" name="CP_W_16B_REQUESTS"/>
+ <value value="166" name="CP_W_32B_REQUESTS"/>
+ <value value="167" name="TC_16B_REQUESTS"/>
+ <value value="168" name="TC_32B_REQUESTS"/>
+ <value value="169" name="PA_REQUESTS"/>
+ <value value="170" name="PA_DATA_BYTES_WRITTEN"/>
+ <value value="171" name="PA_WRITE_CLEAN_RESPONSES"/>
+ <value value="172" name="PA_CYCLES_HELD_OFF"/>
+ <value value="173" name="AXI_READ_REQUEST_DATA_BEATS_ID_0"/>
+ <value value="174" name="AXI_READ_REQUEST_DATA_BEATS_ID_1"/>
+ <value value="175" name="AXI_READ_REQUEST_DATA_BEATS_ID_2"/>
+ <value value="176" name="AXI_READ_REQUEST_DATA_BEATS_ID_3"/>
+ <value value="177" name="AXI_READ_REQUEST_DATA_BEATS_ID_4"/>
+ <value value="178" name="AXI_READ_REQUEST_DATA_BEATS_ID_5"/>
+ <value value="179" name="AXI_READ_REQUEST_DATA_BEATS_ID_6"/>
+ <value value="180" name="AXI_READ_REQUEST_DATA_BEATS_ID_7"/>
+ <value value="181" name="AXI_TOTAL_READ_REQUEST_DATA_BEATS"/>
+</enum>
+
<domain name="A2XX" width="32">
<bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes">
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