Mesa (staging/19.2): radeonsi/gfx10: fix L2 cache rinse programming

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Module: Mesa
Branch: staging/19.2
Commit: 8f95245068ec53d63f96f26384af89443f7d962e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f95245068ec53d63f96f26384af89443f7d962e

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Sep 24 15:15:00 2019 -0400

radeonsi/gfx10: fix L2 cache rinse programming

Cc: 19.2 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 3c0938bece83cd37365c30c35d2d54927f3fe0cd)

---

 src/gallium/drivers/radeonsi/si_state_draw.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 118d87e4734..a8372173b8c 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1130,16 +1130,28 @@ void gfx10_emit_cache_flush(struct si_context *ctx)
 	}
 	if (flags & SI_CONTEXT_INV_VCACHE)
 		gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
+
+	/* The L2 cache ops are:
+	 * - INV: - invalidate lines that reflect memory (were loaded from memory)
+	 *        - don't touch lines that were overwritten (were stored by gfx clients)
+	 * - WB: - don't touch lines that reflect memory
+	 *       - write back lines that were overwritten
+	 * - WB | INV: - invalidate lines that reflect memory
+	 *             - write back lines that were overwritten
+	 *
+	 * GLM doesn't support WB alone. If WB is set, INV must be set too.
+	 */
 	if (flags & SI_CONTEXT_INV_L2) {
 		/* Writeback and invalidate everything in L2. */
-		gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
+		gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
+			    S_586_GLM_INV(1) | S_586_GLM_WB(1);
 		ctx->num_L2_invalidates++;
 	} else if (flags & SI_CONTEXT_WB_L2) {
-		/* Writeback but do not invalidate. */
-		gcr_cntl |= S_586_GL2_WB(1);
+		gcr_cntl |= S_586_GL2_WB(1) |
+			    S_586_GLM_WB(1) | S_586_GLM_INV(1);
+	} else if (flags & SI_CONTEXT_INV_L2_METADATA) {
+		gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
 	}
-	if (flags & SI_CONTEXT_INV_L2_METADATA)
-		gcr_cntl |= S_586_GLM_INV(1);
 
 	if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
 		if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {