Mesa (master): radv/gfx10: fix NGG streamout with triangle strips for VS

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: e19d1ee2d1f0567512c831d02fafb625bbbddbd8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e19d1ee2d1f0567512c831d02fafb625bbbddbd8

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Sep 17 18:52:02 2019 +0200

radv/gfx10: fix NGG streamout with triangle strips for VS

The number of vertices has to be adjusted with the output primitive
type.

This fixes dEQP-VK.transform_feedback.simple.triangle_strip_*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 6 +++++-
 src/amd/vulkan/radv_pipeline.c    | 4 ++++
 src/amd/vulkan/radv_private.h     | 1 +
 src/amd/vulkan/radv_shader.h      | 3 +++
 4 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 46d9ae97049..126251193b1 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3702,7 +3702,11 @@ handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
 	LLVMValueRef num_vertices_val;
 
 	if (ctx->stage == MESA_SHADER_VERTEX) {
-		num_vertices_val = LLVMConstInt(ctx->ac.i32, 1, false);
+		LLVMValueRef outprim_val =
+			LLVMConstInt(ctx->ac.i32,
+				     ctx->options->key.vs.outprim, false);
+		num_vertices_val = LLVMBuildAdd(builder, outprim_val,
+						ctx->ac.i32_1, "");
 		num_vertices = 3; /* TODO: optimize for points & lines */
 	} else {
 		assert(ctx->stage == MESA_SHADER_TESS_EVAL);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1be8d406a43..cc30cb445e4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2263,6 +2263,9 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
 	if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
 		radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
 
+	if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
+		key.topology = pCreateInfo->pInputAssemblyState->topology;
+
 	return key;
 }
 
@@ -2292,6 +2295,7 @@ radv_fill_shader_keys(struct radv_device *device,
 		keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
 		keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
 	}
+	keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
 
 	if (nir[MESA_SHADER_TESS_CTRL]) {
 		keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index f4c32659d79..4babe8b0359 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -378,6 +378,7 @@ struct radv_pipeline_key {
 	uint8_t num_samples;
 	uint32_t has_multiview_view_index : 1;
 	uint32_t optimisations_disabled : 1;
+	uint8_t topology;
 };
 
 struct radv_shader_binary;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 349c1c968ee..aa8a340d2e1 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -76,6 +76,9 @@ struct radv_vs_variant_key {
 
 	/* For some formats the channels have to be shuffled. */
 	uint32_t post_shuffle;
+
+	/* Output primitive type. */
+	uint8_t outprim;
 };
 
 struct radv_tes_variant_key {